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Searched refs:A20R_PT_CLOCK_BASE (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sni/
Dtime.c19 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; in a20r_set_periodic()
21 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV & 0xff; in a20r_set_periodic()
23 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8; in a20r_set_periodic()
26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; in a20r_set_periodic()
28 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV & 0xff; in a20r_set_periodic()
30 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8; in a20r_set_periodic()
/arch/mips/include/asm/
Dsni.h140 #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) macro