Searched refs:ASI_M_FLUSH_CTX (Results 1 – 5 of 5) sorted by relevance
/arch/sparc/mm/ |
D | swift.S | 71 sta %g0, [%o0] ASI_M_FLUSH_CTX 84 1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX 85 sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX 86 sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX 87 sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX 88 sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX 89 sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX 90 sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX 91 sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
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D | hypersparc.S | 34 sta %g0, [%g5] ASI_M_FLUSH_CTX
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/arch/sparc/include/asm/ |
D | swift.h | 102 : "i" (ASI_M_FLUSH_CTX) in swift_flush_context()
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D | ross.h | 159 : "r" (addr), "i" (ASI_M_FLUSH_CTX) in hyper_flush_unconditional_combined()
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/arch/sparc/include/uapi/asm/ |
D | asi.h | 65 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */ macro
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