1 /* 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power management unit definition 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __ASM_ARCH_REGS_PMU_H 13 #define __ASM_ARCH_REGS_PMU_H __FILE__ 14 15 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 16 17 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 18 19 #define S5P_CENTRAL_SEQ_OPTION 0x0208 20 21 #define S5P_USE_STANDBY_WFI0 (1 << 16) 22 #define S5P_USE_STANDBY_WFI1 (1 << 17) 23 #define S5P_USE_STANDBY_WFI2 (1 << 19) 24 #define S5P_USE_STANDBY_WFI3 (1 << 20) 25 #define S5P_USE_STANDBY_WFE0 (1 << 24) 26 #define S5P_USE_STANDBY_WFE1 (1 << 25) 27 #define S5P_USE_STANDBY_WFE2 (1 << 27) 28 #define S5P_USE_STANDBY_WFE3 (1 << 28) 29 30 #define S5P_USE_STANDBY_WFI_ALL \ 31 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \ 32 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \ 33 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \ 34 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3) 35 36 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) 37 38 #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n) 39 #define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) 40 #define EXYNOS_SWRESET 0x0400 41 #define EXYNOS5440_SWRESET 0x00C4 42 43 #define S5P_WAKEUP_STAT 0x0600 44 #define S5P_EINT_WAKEUP_MASK 0x0604 45 #define S5P_WAKEUP_MASK 0x0608 46 #define S5P_WAKEUP_MASK2 0x0614 47 48 #define S5P_INFORM0 0x0800 49 #define S5P_INFORM1 0x0804 50 #define S5P_INFORM5 0x0814 51 #define S5P_INFORM6 0x0818 52 #define S5P_INFORM7 0x081C 53 #define S5P_PMU_SPARE2 0x0908 54 #define S5P_PMU_SPARE3 0x090C 55 56 #define EXYNOS_IROM_DATA2 0x0988 57 #define S5P_ARM_CORE0_LOWPWR 0x1000 58 #define S5P_DIS_IRQ_CORE0 0x1004 59 #define S5P_DIS_IRQ_CENTRAL0 0x1008 60 #define S5P_ARM_CORE1_LOWPWR 0x1010 61 #define S5P_DIS_IRQ_CORE1 0x1014 62 #define S5P_DIS_IRQ_CENTRAL1 0x1018 63 #define S5P_ARM_COMMON_LOWPWR 0x1080 64 #define S5P_L2_0_LOWPWR 0x10C0 65 #define S5P_L2_1_LOWPWR 0x10C4 66 #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 67 #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 68 #define S5P_CMU_RESET_LOWPWR 0x110C 69 #define S5P_APLL_SYSCLK_LOWPWR 0x1120 70 #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 71 #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 72 #define S5P_EPLL_SYSCLK_LOWPWR 0x112C 73 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 74 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C 75 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 76 #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 77 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 78 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C 79 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 80 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 81 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C 82 #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 83 #define S5P_CMU_RESET_TV_LOWPWR 0x1164 84 #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 85 #define S5P_CMU_RESET_G3D_LOWPWR 0x116C 86 #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 87 #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 88 #define S5P_CMU_RESET_GPS_LOWPWR 0x117C 89 #define S5P_TOP_BUS_LOWPWR 0x1180 90 #define S5P_TOP_RETENTION_LOWPWR 0x1184 91 #define S5P_TOP_PWR_LOWPWR 0x1188 92 #define S5P_LOGIC_RESET_LOWPWR 0x11A0 93 #define S5P_ONENAND_MEM_LOWPWR 0x11C0 94 #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 95 #define S5P_USBOTG_MEM_LOWPWR 0x11CC 96 #define S5P_HSMMC_MEM_LOWPWR 0x11D0 97 #define S5P_CSSYS_MEM_LOWPWR 0x11D4 98 #define S5P_SECSS_MEM_LOWPWR 0x11D8 99 #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 100 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 101 #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 102 #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 103 #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 104 #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C 105 #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 106 #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 107 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 108 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 109 #define S5P_XUSBXTI_LOWPWR 0x1280 110 #define S5P_XXTI_LOWPWR 0x1284 111 #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 112 #define S5P_GPIO_MODE_LOWPWR 0x1300 113 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 114 #define S5P_CAM_LOWPWR 0x1380 115 #define S5P_TV_LOWPWR 0x1384 116 #define S5P_MFC_LOWPWR 0x1388 117 #define S5P_G3D_LOWPWR 0x138C 118 #define S5P_LCD0_LOWPWR 0x1390 119 #define S5P_MAUDIO_LOWPWR 0x1398 120 #define S5P_GPS_LOWPWR 0x139C 121 #define S5P_GPS_ALIVE_LOWPWR 0x13A0 122 123 #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 124 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 125 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 126 #define EXYNOS_ARM_CORE_STATUS(_nr) \ 127 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 128 #define EXYNOS_ARM_CORE_OPTION(_nr) \ 129 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) 130 131 #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 132 #define EXYNOS_COMMON_CONFIGURATION(_nr) \ 133 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 134 #define EXYNOS_COMMON_STATUS(_nr) \ 135 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 136 #define EXYNOS_COMMON_OPTION(_nr) \ 137 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 138 139 #define EXYNOS_CORE_LOCAL_PWR_EN 0x3 140 141 #define EXYNOS_ARM_COMMON_STATUS 0x2504 142 #define EXYNOS_COMMON_OPTION(_nr) \ 143 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 144 145 #define EXYNOS_ARM_L2_CONFIGURATION 0x2600 146 #define EXYNOS_L2_CONFIGURATION(_nr) \ 147 (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) 148 #define EXYNOS_L2_STATUS(_nr) \ 149 (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) 150 #define EXYNOS_L2_OPTION(_nr) \ 151 (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) 152 #define EXYNOS_L2_COMMON_PWR_EN 0x3 153 154 #define EXYNOS_ARM_CORE_X_STATUS_OFFSET 0x4 155 156 #define EXYNOS5_APLL_SYSCLK_CONFIGURATION 0x2A00 157 #define EXYNOS5_APLL_SYSCLK_STATUS 0x2A04 158 159 #define EXYNOS5_ARM_L2_OPTION 0x2608 160 #define EXYNOS5_USE_RETENTION BIT(4) 161 162 #define EXYNOS5_L2RSTDISABLE_VALUE BIT(3) 163 164 #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 165 #define S5P_PAD_RET_MMC2_OPTION 0x30c8 166 #define S5P_PAD_RET_GPIO_OPTION 0x3108 167 #define S5P_PAD_RET_UART_OPTION 0x3128 168 #define S5P_PAD_RET_MMCA_OPTION 0x3148 169 #define S5P_PAD_RET_MMCB_OPTION 0x3168 170 #define S5P_PAD_RET_EBIA_OPTION 0x3188 171 #define S5P_PAD_RET_EBIB_OPTION 0x31A8 172 #define S5P_PAD_RET_SPI_OPTION 0x31c8 173 174 #define S5P_PS_HOLD_CONTROL 0x330C 175 #define S5P_PS_HOLD_EN (1 << 31) 176 #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) 177 178 #define S5P_CAM_OPTION 0x3C08 179 #define S5P_MFC_OPTION 0x3C48 180 #define S5P_G3D_OPTION 0x3C68 181 #define S5P_LCD0_OPTION 0x3C88 182 #define S5P_LCD1_OPTION 0x3CA8 183 #define S5P_ISP_OPTION S5P_LCD1_OPTION 184 185 #define S5P_CORE_LOCAL_PWR_EN 0x3 186 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) 187 #define S5P_CORE_AUTOWAKEUP_EN (1 << 31) 188 189 /* Only for EXYNOS4210 */ 190 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 191 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 192 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 193 #define S5P_PCIE_MEM_LOWPWR 0x11E0 194 #define S5P_SATA_MEM_LOWPWR 0x11E4 195 #define S5P_LCD1_LOWPWR 0x1394 196 197 /* Only for EXYNOS4x12 */ 198 #define S5P_ISP_ARM_LOWPWR 0x1050 199 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 200 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 201 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 202 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 203 #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C 204 #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 205 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 206 #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 207 #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 208 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 209 #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 210 #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 211 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 212 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 213 #define S5P_HSI_MEM_LOWPWR 0x11C4 214 #define S5P_ROTATOR_MEM_LOWPWR 0x11DC 215 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C 216 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 217 #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 218 #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 219 #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 220 #define S5P_ISP_LOWPWR 0x1394 221 #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 222 #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 223 #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 224 #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC 225 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 226 227 #define S5P_ARM_L2_0_OPTION 0x2608 228 #define S5P_ARM_L2_1_OPTION 0x2628 229 #define S5P_ONENAND_MEM_OPTION 0x2E08 230 #define S5P_HSI_MEM_OPTION 0x2E28 231 #define S5P_G2D_ACP_MEM_OPTION 0x2E48 232 #define S5P_USBOTG_MEM_OPTION 0x2E68 233 #define S5P_HSMMC_MEM_OPTION 0x2E88 234 #define S5P_CSSYS_MEM_OPTION 0x2EA8 235 #define S5P_SECSS_MEM_OPTION 0x2EC8 236 #define S5P_ROTATOR_MEM_OPTION 0x2F48 237 238 /* Only for EXYNOS4412 */ 239 #define S5P_ARM_CORE2_LOWPWR 0x1020 240 #define S5P_DIS_IRQ_CORE2 0x1024 241 #define S5P_DIS_IRQ_CENTRAL2 0x1028 242 #define S5P_ARM_CORE3_LOWPWR 0x1030 243 #define S5P_DIS_IRQ_CORE3 0x1034 244 #define S5P_DIS_IRQ_CENTRAL3 0x1038 245 246 /* Only for EXYNOS3XXX */ 247 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000 248 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 249 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 250 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010 251 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 252 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 253 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050 254 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 255 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 256 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080 257 #define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0 258 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 259 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 260 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C 261 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110 262 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114 263 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C 264 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120 265 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124 266 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128 267 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C 268 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130 269 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134 270 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138 271 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 272 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 273 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C 274 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 275 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154 276 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 277 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160 278 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168 279 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C 280 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170 281 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174 282 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 283 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180 284 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184 285 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188 286 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190 287 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194 288 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198 289 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0 290 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4 291 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0 292 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4 293 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 294 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 295 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208 296 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 297 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 298 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 299 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 300 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C 301 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 302 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 303 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238 304 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240 305 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260 306 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280 307 #define EXYNOS3_XXTI_SYS_PWR_REG 0x1284 308 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0 309 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4 310 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300 311 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 312 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344 313 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 314 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350 315 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354 316 #define EXYNOS3_CAM_SYS_PWR_REG 0x1380 317 #define EXYNOS3_MFC_SYS_PWR_REG 0x1388 318 #define EXYNOS3_G3D_SYS_PWR_REG 0x138C 319 #define EXYNOS3_LCD0_SYS_PWR_REG 0x1390 320 #define EXYNOS3_ISP_SYS_PWR_REG 0x1394 321 #define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398 322 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0 323 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4 324 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8 325 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0 326 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4 327 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8 328 329 #define EXYNOS3_ARM_CORE0_OPTION 0x2008 330 #define EXYNOS3_ARM_CORE_OPTION(_nr) \ 331 (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80)) 332 333 #define EXYNOS3_ARM_COMMON_OPTION 0x2408 334 #define EXYNOS3_ARM_L2_OPTION 0x2608 335 #define EXYNOS3_TOP_PWR_OPTION 0x2C48 336 #define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8 337 #define EXYNOS3_XUSBXTI_DURATION 0x341C 338 #define EXYNOS3_XXTI_DURATION 0x343C 339 #define EXYNOS3_EXT_REGULATOR_DURATION 0x361C 340 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C 341 #define XUSBXTI_DURATION 0x00000BB8 342 #define XXTI_DURATION XUSBXTI_DURATION 343 #define EXT_REGULATOR_DURATION 0x00001D4C 344 #define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION 345 346 /* for XXX_OPTION */ 347 #define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0) 348 #define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1) 349 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 350 351 /* For EXYNOS5 */ 352 353 #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 354 #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C 355 356 #define EXYNOS5_USE_RETENTION BIT(4) 357 #define EXYNOS5_SYS_WDTRESET (1 << 20) 358 359 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 360 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 361 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 362 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 363 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 364 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 365 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 366 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 367 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 368 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 369 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 370 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 371 #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 372 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 373 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 374 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C 375 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 376 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 377 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C 378 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 379 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 380 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 381 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 382 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 383 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 384 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C 385 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 386 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 387 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 388 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 389 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 390 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 391 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 392 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 393 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 394 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 395 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 396 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 397 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 398 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 399 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 400 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 401 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC 402 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 403 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 404 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 405 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC 406 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 407 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 408 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 409 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC 410 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 411 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC 412 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 413 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 414 #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208 415 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 416 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 417 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 418 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C 419 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 420 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 421 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 422 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C 423 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 424 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 425 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 426 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 427 #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 428 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 429 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 430 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 431 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 432 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 433 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 434 #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 435 #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 436 #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 437 #define EXYNOS5_G3D_SYS_PWR_REG 0x140C 438 #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 439 #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 440 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 441 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 442 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 443 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C 444 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 445 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 446 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 447 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 448 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 449 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC 450 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 451 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 452 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 453 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 454 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 455 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C 456 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 457 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 458 459 #define EXYNOS5_ARM_CORE0_OPTION 0x2008 460 #define EXYNOS5_ARM_CORE1_OPTION 0x2088 461 #define EXYNOS5_FSYS_ARM_OPTION 0x2208 462 #define EXYNOS5_ISP_ARM_OPTION 0x2288 463 #define EXYNOS5_ARM_COMMON_OPTION 0x2408 464 #define EXYNOS5_ARM_L2_OPTION 0x2608 465 #define EXYNOS5_TOP_PWR_OPTION 0x2C48 466 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 467 #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 468 #define EXYNOS5_GSCL_OPTION 0x4008 469 #define EXYNOS5_ISP_OPTION 0x4028 470 #define EXYNOS5_MFC_OPTION 0x4048 471 #define EXYNOS5_G3D_OPTION 0x4068 472 #define EXYNOS5_DISP1_OPTION 0x40A8 473 #define EXYNOS5_MAU_OPTION 0x40C8 474 475 #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 476 #define EXYNOS5_USE_SC_COUNTER (1 << 0) 477 478 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 479 480 #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) 481 #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) 482 483 #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) 484 485 #define EXYNOS5420_SWRESET_KFC_SEL 0x3 486 487 #include <asm/cputype.h> 488 #define MAX_CPUS_IN_CLUSTER 4 489 exynos_pmu_cpunr(unsigned int mpidr)490static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) 491 { 492 return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) 493 + MPIDR_AFFINITY_LEVEL(mpidr, 0)); 494 } 495 496 /* Only for EXYNOS5420 */ 497 #define EXYNOS5420_ISP_ARM_OPTION 0x2488 498 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) 499 500 #define EXYNOS5420_LPI_MASK 0x0004 501 #define EXYNOS5420_LPI_MASK1 0x0008 502 #define EXYNOS5420_UFS BIT(8) 503 #define EXYNOS5420_ATB_KFC BIT(13) 504 #define EXYNOS5420_ATB_ISP_ARM BIT(19) 505 #define EXYNOS5420_EMULATION BIT(31) 506 #define ATB_ISP_ARM BIT(12) 507 #define ATB_KFC BIT(13) 508 #define ATB_NOC BIT(14) 509 510 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 511 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 512 #define EXYNOS5420_UP_SCHEDULER 0x0120 513 #define SPREAD_ENABLE 0xF 514 #define SPREAD_USE_STANDWFI 0xF 515 516 #define EXYNOS5420_KFC_CORE_RESET0 BIT(8) 517 #define EXYNOS5420_KFC_ETM_RESET0 BIT(20) 518 519 #define EXYNOS5420_KFC_CORE_RESET(_nr) \ 520 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) 521 522 #define EXYNOS5420_BB_CON1 0x0784 523 #define EXYNOS5420_BB_SEL_EN BIT(31) 524 #define EXYNOS5420_BB_PMOS_EN BIT(7) 525 #define EXYNOS5420_BB_1300X 0XF 526 527 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 528 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 529 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 530 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 531 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 532 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 533 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 534 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 535 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 536 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 537 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 538 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 539 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 540 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 541 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 542 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 543 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 544 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 545 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 546 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 547 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 548 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 549 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 550 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 551 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 552 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C 553 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 554 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 555 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 556 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 557 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC 558 #define EXYNOS5420_ONENANDXL_MEM_SYS_PWR 0x11C0 559 #define EXYNOS5420_USBDEV_MEM_SYS_PWR 0x11CC 560 #define EXYNOS5420_USBDEV1_MEM_SYS_PWR 0x11D0 561 #define EXYNOS5420_SDMMC_MEM_SYS_PWR 0x11D4 562 #define EXYNOS5420_CSSYS_MEM_SYS_PWR 0x11D8 563 #define EXYNOS5420_SECSS_MEM_SYS_PWR 0x11DC 564 #define EXYNOS5420_ROTATOR_MEM_SYS_PWR 0x11E0 565 #define EXYNOS5420_INTRAM_MEM_SYS_PWR 0x11E4 566 #define EXYNOS5420_INTROM_MEM_SYS_PWR 0x11E8 567 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 568 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 569 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 570 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 571 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C 572 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 573 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 574 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 575 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C 576 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 577 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 578 #define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 579 #define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 580 #define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 581 #define EXYNOS5420_MSC_SYS_PWR_REG 0x141C 582 #define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 583 #define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 584 #define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 585 #define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C 586 #define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 587 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 588 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 589 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 590 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C 591 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 592 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 593 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 594 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC 595 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 596 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC 597 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 598 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 599 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 600 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC 601 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 602 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 603 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 604 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC 605 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 606 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 607 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 608 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 609 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 610 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C 611 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 612 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 613 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 614 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C 615 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 616 #define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 617 #define EXYNOS_ARM_CORE2_CONFIGURATION 0x2100 618 #define EXYNOS5420_ARM_CORE2_OPTION 0x2108 619 #define EXYNOS_ARM_CORE3_CONFIGURATION 0x2180 620 #define EXYNOS5420_ARM_CORE3_OPTION 0x2188 621 #define EXYNOS5420_ARM_COMMON_STATUS 0x2504 622 #define EXYNOS5420_ARM_COMMON_OPTION 0x2508 623 #define EXYNOS5420_KFC_COMMON_STATUS 0x2584 624 #define EXYNOS5420_KFC_COMMON_OPTION 0x2588 625 #define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C 626 627 #define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 628 #define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 629 #define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 630 #define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 631 #define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 632 #define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 633 #define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 634 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 635 #define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 636 #define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 637 #define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 638 #define EXYNOS_PAD_RET_GPIO_OPTION 0x3108 639 #define EXYNOS_PAD_RET_UART_OPTION 0x3128 640 #define EXYNOS_PAD_RET_MMCA_OPTION 0x3148 641 #define EXYNOS_PAD_RET_MMCB_OPTION 0x3168 642 #define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 643 #define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 644 645 #define EXYNOS_PS_HOLD_CONTROL 0x330C 646 647 /* For SYS_PWR_REG */ 648 #define EXYNOS_SYS_PWR_CFG BIT(0) 649 650 #define EXYNOS5420_MFC_CONFIGURATION 0x4060 651 #define EXYNOS5420_MFC_STATUS 0x4064 652 #define EXYNOS5420_MFC_OPTION 0x4068 653 #define EXYNOS5420_G3D_CONFIGURATION 0x4080 654 #define EXYNOS5420_G3D_STATUS 0x4084 655 #define EXYNOS5420_G3D_OPTION 0x4088 656 #define EXYNOS5420_DISP0_CONFIGURATION 0x40A0 657 #define EXYNOS5420_DISP0_STATUS 0x40A4 658 #define EXYNOS5420_DISP0_OPTION 0x40A8 659 #define EXYNOS5420_DISP1_CONFIGURATION 0x40C0 660 #define EXYNOS5420_DISP1_STATUS 0x40C4 661 #define EXYNOS5420_DISP1_OPTION 0x40C8 662 #define EXYNOS5420_MAU_CONFIGURATION 0x40E0 663 #define EXYNOS5420_MAU_STATUS 0x40E4 664 #define EXYNOS5420_MAU_OPTION 0x40E8 665 #define EXYNOS5420_FSYS2_OPTION 0x4168 666 #define EXYNOS5420_PSGEN_OPTION 0x4188 667 668 /* For EXYNOS_CENTRAL_SEQ_OPTION */ 669 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16) 670 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17) 671 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24) 672 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25) 673 674 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) 675 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) 676 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) 677 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) 678 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) 679 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) 680 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) 681 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) 682 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) 683 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) 684 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) 685 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) 686 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) 687 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) 688 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) 689 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) 690 691 #define DUR_WAIT_RESET 0xF 692 693 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ 694 | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ 695 | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ 696 | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ 697 | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ 698 | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ 699 | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ 700 | EXYNOS5420_KFC_USE_STANDBY_WFI3) 701 702 #endif /* __ASM_ARCH_REGS_PMU_H */ 703