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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
7  * revision 1.76.
8  *
9  * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
10  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
11  */
12 #ifndef _ASM_PCI_BRIDGE_H
13 #define _ASM_PCI_BRIDGE_H
14 
15 #include <linux/types.h>
16 #include <linux/pci.h>
17 #include <asm/xtalk/xwidget.h>		/* generic widget header */
18 #include <asm/sn/types.h>
19 
20 /* I/O page size */
21 
22 #define IOPFNSHIFT		12	/* 4K per mapped page */
23 
24 #define IOPGSIZE		(1 << IOPFNSHIFT)
25 #define IOPG(x)			((x) >> IOPFNSHIFT)
26 #define IOPGOFF(x)		((x) & (IOPGSIZE-1))
27 
28 /* Bridge RAM sizes */
29 
30 #define BRIDGE_ATE_RAM_SIZE	0x00000400	/* 1kB ATE RAM */
31 
32 #define BRIDGE_CONFIG_BASE	0x20000
33 #define BRIDGE_CONFIG1_BASE	0x28000
34 #define BRIDGE_CONFIG_END	0x30000
35 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
36 
37 #define BRIDGE_SSRAM_512K	0x00080000	/* 512kB */
38 #define BRIDGE_SSRAM_128K	0x00020000	/* 128kB */
39 #define BRIDGE_SSRAM_64K	0x00010000	/* 64kB */
40 #define BRIDGE_SSRAM_0K		0x00000000	/* 0kB */
41 
42 /* ========================================================================
43  *    Bridge address map
44  */
45 
46 #ifndef __ASSEMBLY__
47 
48 /*
49  * All accesses to bridge hardware registers must be done
50  * using 32-bit loads and stores.
51  */
52 typedef u32	bridgereg_t;
53 
54 typedef u64	bridge_ate_t;
55 
56 /* pointers to bridge ATEs
57  * are always "pointer to volatile"
58  */
59 typedef volatile bridge_ate_t  *bridge_ate_p;
60 
61 /*
62  * It is generally preferred that hardware registers on the bridge
63  * are located from C code via this structure.
64  *
65  * Generated from Bridge spec dated 04oct95
66  */
67 
68 typedef volatile struct bridge_s {
69 	/* Local Registers			       0x000000-0x00FFFF */
70 
71 	/* standard widget configuration	       0x000000-0x000057 */
72 	widget_cfg_t	    b_widget;			/* 0x000000 */
73 
74 	/* helper fieldnames for accessing bridge widget */
75 
76 #define b_wid_id			b_widget.w_id
77 #define b_wid_stat			b_widget.w_status
78 #define b_wid_err_upper			b_widget.w_err_upper_addr
79 #define b_wid_err_lower			b_widget.w_err_lower_addr
80 #define b_wid_control			b_widget.w_control
81 #define b_wid_req_timeout		b_widget.w_req_timeout
82 #define b_wid_int_upper			b_widget.w_intdest_upper_addr
83 #define b_wid_int_lower			b_widget.w_intdest_lower_addr
84 #define b_wid_err_cmdword		b_widget.w_err_cmd_word
85 #define b_wid_llp			b_widget.w_llp_cfg
86 #define b_wid_tflush			b_widget.w_tflush
87 
88 	/* bridge-specific widget configuration 0x000058-0x00007F */
89 	bridgereg_t	    _pad_000058;
90 	bridgereg_t	    b_wid_aux_err;		/* 0x00005C */
91 	bridgereg_t	    _pad_000060;
92 	bridgereg_t	    b_wid_resp_upper;		/* 0x000064 */
93 	bridgereg_t	    _pad_000068;
94 	bridgereg_t	    b_wid_resp_lower;		/* 0x00006C */
95 	bridgereg_t	    _pad_000070;
96 	bridgereg_t	    b_wid_tst_pin_ctrl;		/* 0x000074 */
97 	bridgereg_t	_pad_000078[2];
98 
99 	/* PMU & Map 0x000080-0x00008F */
100 	bridgereg_t	_pad_000080;
101 	bridgereg_t	b_dir_map;			/* 0x000084 */
102 	bridgereg_t	_pad_000088[2];
103 
104 	/* SSRAM 0x000090-0x00009F */
105 	bridgereg_t	_pad_000090;
106 	bridgereg_t	b_ram_perr;			/* 0x000094 */
107 	bridgereg_t	_pad_000098[2];
108 
109 	/* Arbitration 0x0000A0-0x0000AF */
110 	bridgereg_t	_pad_0000A0;
111 	bridgereg_t	b_arb;				/* 0x0000A4 */
112 	bridgereg_t	_pad_0000A8[2];
113 
114 	/* Number In A Can 0x0000B0-0x0000BF */
115 	bridgereg_t	_pad_0000B0;
116 	bridgereg_t	b_nic;				/* 0x0000B4 */
117 	bridgereg_t	_pad_0000B8[2];
118 
119 	/* PCI/GIO 0x0000C0-0x0000FF */
120 	bridgereg_t	_pad_0000C0;
121 	bridgereg_t	b_bus_timeout;			/* 0x0000C4 */
122 #define b_pci_bus_timeout b_bus_timeout
123 
124 	bridgereg_t	_pad_0000C8;
125 	bridgereg_t	b_pci_cfg;			/* 0x0000CC */
126 	bridgereg_t	_pad_0000D0;
127 	bridgereg_t	b_pci_err_upper;		/* 0x0000D4 */
128 	bridgereg_t	_pad_0000D8;
129 	bridgereg_t	b_pci_err_lower;		/* 0x0000DC */
130 	bridgereg_t	_pad_0000E0[8];
131 #define b_gio_err_lower b_pci_err_lower
132 #define b_gio_err_upper b_pci_err_upper
133 
134 	/* Interrupt 0x000100-0x0001FF */
135 	bridgereg_t	_pad_000100;
136 	bridgereg_t	b_int_status;			/* 0x000104 */
137 	bridgereg_t	_pad_000108;
138 	bridgereg_t	b_int_enable;			/* 0x00010C */
139 	bridgereg_t	_pad_000110;
140 	bridgereg_t	b_int_rst_stat;			/* 0x000114 */
141 	bridgereg_t	_pad_000118;
142 	bridgereg_t	b_int_mode;			/* 0x00011C */
143 	bridgereg_t	_pad_000120;
144 	bridgereg_t	b_int_device;			/* 0x000124 */
145 	bridgereg_t	_pad_000128;
146 	bridgereg_t	b_int_host_err;			/* 0x00012C */
147 
148 	struct {
149 		bridgereg_t	__pad;			/* 0x0001{30,,,68} */
150 		bridgereg_t	addr;			/* 0x0001{34,,,6C} */
151 	} b_int_addr[8];				/* 0x000130 */
152 
153 	bridgereg_t	_pad_000170[36];
154 
155 	/* Device 0x000200-0x0003FF */
156 	struct {
157 		bridgereg_t	__pad;			/* 0x0002{00,,,38} */
158 		bridgereg_t	reg;			/* 0x0002{04,,,3C} */
159 	} b_device[8];					/* 0x000200 */
160 
161 	struct {
162 		bridgereg_t	__pad;			/* 0x0002{40,,,78} */
163 		bridgereg_t	reg;			/* 0x0002{44,,,7C} */
164 	} b_wr_req_buf[8];				/* 0x000240 */
165 
166 	struct {
167 		bridgereg_t	__pad;			/* 0x0002{80,,,88} */
168 		bridgereg_t	reg;			/* 0x0002{84,,,8C} */
169 	} b_rrb_map[2];					/* 0x000280 */
170 #define b_even_resp	b_rrb_map[0].reg		/* 0x000284 */
171 #define b_odd_resp	b_rrb_map[1].reg		/* 0x00028C */
172 
173 	bridgereg_t	_pad_000290;
174 	bridgereg_t	b_resp_status;			/* 0x000294 */
175 	bridgereg_t	_pad_000298;
176 	bridgereg_t	b_resp_clear;			/* 0x00029C */
177 
178 	bridgereg_t	_pad_0002A0[24];
179 
180 	char		_pad_000300[0x10000 - 0x000300];
181 
182 	/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
183 	union {
184 		bridge_ate_t	wr;			/* write-only */
185 		struct {
186 			bridgereg_t	_p_pad;
187 			bridgereg_t	rd;		/* read-only */
188 		}			hi;
189 	}			    b_int_ate_ram[128];
190 
191 	char	_pad_010400[0x11000 - 0x010400];
192 
193 	/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
194 	struct {
195 		bridgereg_t	_p_pad;
196 		bridgereg_t	rd;		/* read-only */
197 	} b_int_ate_ram_lo[128];
198 
199 	char	_pad_011400[0x20000 - 0x011400];
200 
201 	/* PCI Device Configuration Spaces 0x020000-0x027FFF */
202 	union {				/* make all access sizes available. */
203 		u8	c[0x1000 / 1];
204 		u16	s[0x1000 / 2];
205 		u32	l[0x1000 / 4];
206 		u64	d[0x1000 / 8];
207 		union {
208 			u8	c[0x100 / 1];
209 			u16	s[0x100 / 2];
210 			u32	l[0x100 / 4];
211 			u64	d[0x100 / 8];
212 		} f[8];
213 	} b_type0_cfg_dev[8];					/* 0x020000 */
214 
215     /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
216 	union {				/* make all access sizes available. */
217 		u8	c[0x1000 / 1];
218 		u16	s[0x1000 / 2];
219 		u32	l[0x1000 / 4];
220 		u64	d[0x1000 / 8];
221 	} b_type1_cfg;					/* 0x028000-0x029000 */
222 
223 	char	_pad_029000[0x007000];			/* 0x029000-0x030000 */
224 
225 	/* PCI Interrupt Acknowledge Cycle 0x030000 */
226 	union {
227 		u8	c[8 / 1];
228 		u16	s[8 / 2];
229 		u32	l[8 / 4];
230 		u64	d[8 / 8];
231 	} b_pci_iack;						/* 0x030000 */
232 
233 	u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */
234 
235 	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
236 	bridge_ate_t	b_ext_ate_ram[0x10000];
237 
238 	/* Reserved 0x100000-0x1FFFFF */
239 	char	_pad_100000[0x200000-0x100000];
240 
241 	/* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
242 	union {				/* make all access sizes available. */
243 		u8	c[0x100000 / 1];
244 		u16	s[0x100000 / 2];
245 		u32	l[0x100000 / 4];
246 		u64	d[0x100000 / 8];
247 	} b_devio_raw[10];				/* 0x200000 */
248 
249 	/* b_devio macro is a bit strange; it reflects the
250 	 * fact that the Bridge ASIC provides 2M for the
251 	 * first two DevIO windows and 1M for the other six.
252 	 */
253 #define b_devio(n)	b_devio_raw[((n)<2)?(n*2):(n+2)]
254 
255 	/* External Flash Proms 1,0 0xC00000-0xFFFFFF */
256 	union {		/* make all access sizes available. */
257 		u8	c[0x400000 / 1];	/* read-only */
258 		u16	s[0x400000 / 2];	/* read-write */
259 		u32	l[0x400000 / 4];	/* read-only */
260 		u64	d[0x400000 / 8];	/* read-only */
261 	} b_external_flash;			/* 0xC00000 */
262 } bridge_t;
263 
264 /*
265  * Field formats for Error Command Word and Auxiliary Error Command Word
266  * of bridge.
267  */
268 typedef struct bridge_err_cmdword_s {
269 	union {
270 		u32		cmd_word;
271 		struct {
272 			u32	didn:4,		/* Destination ID  */
273 				sidn:4,		/* Source ID	   */
274 				pactyp:4,	/* Packet type	   */
275 				tnum:5,		/* Trans Number	   */
276 				coh:1,		/* Coh Transaction */
277 				ds:2,		/* Data size	   */
278 				gbr:1,		/* GBR enable	   */
279 				vbpm:1,		/* VBPM message	   */
280 				error:1,	/* Error occurred  */
281 				barr:1,		/* Barrier op	   */
282 				rsvd:8;
283 		} berr_st;
284 	} berr_un;
285 } bridge_err_cmdword_t;
286 
287 #define berr_field	berr_un.berr_st
288 #endif /* !__ASSEMBLY__ */
289 
290 /*
291  * The values of these macros can and should be crosschecked
292  * regularly against the offsets of the like-named fields
293  * within the "bridge_t" structure above.
294  */
295 
296 /* Byte offset macros for Bridge internal registers */
297 
298 #define BRIDGE_WID_ID		WIDGET_ID
299 #define BRIDGE_WID_STAT		WIDGET_STATUS
300 #define BRIDGE_WID_ERR_UPPER	WIDGET_ERR_UPPER_ADDR
301 #define BRIDGE_WID_ERR_LOWER	WIDGET_ERR_LOWER_ADDR
302 #define BRIDGE_WID_CONTROL	WIDGET_CONTROL
303 #define BRIDGE_WID_REQ_TIMEOUT	WIDGET_REQ_TIMEOUT
304 #define BRIDGE_WID_INT_UPPER	WIDGET_INTDEST_UPPER_ADDR
305 #define BRIDGE_WID_INT_LOWER	WIDGET_INTDEST_LOWER_ADDR
306 #define BRIDGE_WID_ERR_CMDWORD	WIDGET_ERR_CMD_WORD
307 #define BRIDGE_WID_LLP		WIDGET_LLP_CFG
308 #define BRIDGE_WID_TFLUSH	WIDGET_TFLUSH
309 
310 #define BRIDGE_WID_AUX_ERR	0x00005C	/* Aux Error Command Word */
311 #define BRIDGE_WID_RESP_UPPER	0x000064	/* Response Buf Upper Addr */
312 #define BRIDGE_WID_RESP_LOWER	0x00006C	/* Response Buf Lower Addr */
313 #define BRIDGE_WID_TST_PIN_CTRL 0x000074	/* Test pin control */
314 
315 #define BRIDGE_DIR_MAP		0x000084	/* Direct Map reg */
316 
317 #define BRIDGE_RAM_PERR		0x000094	/* SSRAM Parity Error */
318 
319 #define BRIDGE_ARB		0x0000A4	/* Arbitration Priority reg */
320 
321 #define BRIDGE_NIC		0x0000B4	/* Number In A Can */
322 
323 #define BRIDGE_BUS_TIMEOUT	0x0000C4	/* Bus Timeout Register */
324 #define BRIDGE_PCI_BUS_TIMEOUT	BRIDGE_BUS_TIMEOUT
325 #define BRIDGE_PCI_CFG		0x0000CC	/* PCI Type 1 Config reg */
326 #define BRIDGE_PCI_ERR_UPPER	0x0000D4	/* PCI error Upper Addr */
327 #define BRIDGE_PCI_ERR_LOWER	0x0000DC	/* PCI error Lower Addr */
328 
329 #define BRIDGE_INT_STATUS	0x000104	/* Interrupt Status */
330 #define BRIDGE_INT_ENABLE	0x00010C	/* Interrupt Enables */
331 #define BRIDGE_INT_RST_STAT	0x000114	/* Reset Intr Status */
332 #define BRIDGE_INT_MODE		0x00011C	/* Interrupt Mode */
333 #define BRIDGE_INT_DEVICE	0x000124	/* Interrupt Device */
334 #define BRIDGE_INT_HOST_ERR	0x00012C	/* Host Error Field */
335 
336 #define BRIDGE_INT_ADDR0	0x000134	/* Host Address Reg */
337 #define BRIDGE_INT_ADDR_OFF	0x000008	/* Host Addr offset (1..7) */
338 #define BRIDGE_INT_ADDR(x)	(BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
339 
340 #define BRIDGE_DEVICE0		0x000204	/* Device 0 */
341 #define BRIDGE_DEVICE_OFF	0x000008	/* Device offset (1..7) */
342 #define BRIDGE_DEVICE(x)	(BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
343 
344 #define BRIDGE_WR_REQ_BUF0	0x000244	/* Write Request Buffer 0 */
345 #define BRIDGE_WR_REQ_BUF_OFF	0x000008	/* Buffer Offset (1..7) */
346 #define BRIDGE_WR_REQ_BUF(x)	(BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
347 
348 #define BRIDGE_EVEN_RESP	0x000284	/* Even Device Response Buf */
349 #define BRIDGE_ODD_RESP		0x00028C	/* Odd Device Response Buf */
350 
351 #define BRIDGE_RESP_STATUS	0x000294	/* Read Response Status reg */
352 #define BRIDGE_RESP_CLEAR	0x00029C	/* Read Response Clear reg */
353 
354 /* Byte offset macros for Bridge I/O space */
355 
356 #define BRIDGE_ATE_RAM		0x00010000	/* Internal Addr Xlat Ram */
357 
358 #define BRIDGE_TYPE0_CFG_DEV0	0x00020000	/* Type 0 Cfg, Device 0 */
359 #define BRIDGE_TYPE0_CFG_SLOT_OFF	0x00001000	/* Type 0 Cfg Slot Offset (1..7) */
360 #define BRIDGE_TYPE0_CFG_FUNC_OFF	0x00000100	/* Type 0 Cfg Func Offset (1..7) */
361 #define BRIDGE_TYPE0_CFG_DEV(s)		(BRIDGE_TYPE0_CFG_DEV0+\
362 					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
363 #define BRIDGE_TYPE0_CFG_DEVF(s, f)	(BRIDGE_TYPE0_CFG_DEV0+\
364 					 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
365 					 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
366 
367 #define BRIDGE_TYPE1_CFG	0x00028000	/* Type 1 Cfg space */
368 
369 #define BRIDGE_PCI_IACK		0x00030000	/* PCI Interrupt Ack */
370 #define BRIDGE_EXT_SSRAM	0x00080000	/* Extern SSRAM (ATE) */
371 
372 /* Byte offset macros for Bridge device IO spaces */
373 
374 #define BRIDGE_DEV_CNT		8	/* Up to 8 devices per bridge */
375 #define BRIDGE_DEVIO0		0x00200000	/* Device IO 0 Addr */
376 #define BRIDGE_DEVIO1		0x00400000	/* Device IO 1 Addr */
377 #define BRIDGE_DEVIO2		0x00600000	/* Device IO 2 Addr */
378 #define BRIDGE_DEVIO_OFF	0x00100000	/* Device IO Offset (3..7) */
379 
380 #define BRIDGE_DEVIO_2MB	0x00200000	/* Device IO Offset (0..1) */
381 #define BRIDGE_DEVIO_1MB	0x00100000	/* Device IO Offset (2..7) */
382 
383 #define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
384 
385 #define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS */
386 
387 /* ========================================================================
388  *    Bridge register bit field definitions
389  */
390 
391 /* Widget part number of bridge */
392 #define BRIDGE_WIDGET_PART_NUM		0xc002
393 #define XBRIDGE_WIDGET_PART_NUM		0xd002
394 
395 /* Manufacturer of bridge */
396 #define BRIDGE_WIDGET_MFGR_NUM		0x036
397 #define XBRIDGE_WIDGET_MFGR_NUM		0x024
398 
399 /* Revision numbers for known Bridge revisions */
400 #define BRIDGE_REV_A			0x1
401 #define BRIDGE_REV_B			0x2
402 #define BRIDGE_REV_C			0x3
403 #define BRIDGE_REV_D			0x4
404 
405 /* Bridge widget status register bits definition */
406 
407 #define BRIDGE_STAT_LLP_REC_CNT		(0xFFu << 24)
408 #define BRIDGE_STAT_LLP_TX_CNT		(0xFF << 16)
409 #define BRIDGE_STAT_FLASH_SELECT	(0x1 << 6)
410 #define BRIDGE_STAT_PCI_GIO_N		(0x1 << 5)
411 #define BRIDGE_STAT_PENDING		(0x1F << 0)
412 
413 /* Bridge widget control register bits definition */
414 #define BRIDGE_CTRL_FLASH_WR_EN		(0x1ul << 31)
415 #define BRIDGE_CTRL_EN_CLK50		(0x1 << 30)
416 #define BRIDGE_CTRL_EN_CLK40		(0x1 << 29)
417 #define BRIDGE_CTRL_EN_CLK33		(0x1 << 28)
418 #define BRIDGE_CTRL_RST(n)		((n) << 24)
419 #define BRIDGE_CTRL_RST_MASK		(BRIDGE_CTRL_RST(0xF))
420 #define BRIDGE_CTRL_RST_PIN(x)		(BRIDGE_CTRL_RST(0x1 << (x)))
421 #define BRIDGE_CTRL_IO_SWAP		(0x1 << 23)
422 #define BRIDGE_CTRL_MEM_SWAP		(0x1 << 22)
423 #define BRIDGE_CTRL_PAGE_SIZE		(0x1 << 21)
424 #define BRIDGE_CTRL_SS_PAR_BAD		(0x1 << 20)
425 #define BRIDGE_CTRL_SS_PAR_EN		(0x1 << 19)
426 #define BRIDGE_CTRL_SSRAM_SIZE(n)	((n) << 17)
427 #define BRIDGE_CTRL_SSRAM_SIZE_MASK	(BRIDGE_CTRL_SSRAM_SIZE(0x3))
428 #define BRIDGE_CTRL_SSRAM_512K		(BRIDGE_CTRL_SSRAM_SIZE(0x3))
429 #define BRIDGE_CTRL_SSRAM_128K		(BRIDGE_CTRL_SSRAM_SIZE(0x2))
430 #define BRIDGE_CTRL_SSRAM_64K		(BRIDGE_CTRL_SSRAM_SIZE(0x1))
431 #define BRIDGE_CTRL_SSRAM_1K		(BRIDGE_CTRL_SSRAM_SIZE(0x0))
432 #define BRIDGE_CTRL_F_BAD_PKT		(0x1 << 16)
433 #define BRIDGE_CTRL_LLP_XBAR_CRD(n)	((n) << 12)
434 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK	(BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
435 #define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)
436 #define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)
437 #define BRIDGE_CTRL_SYS_END		(0x1 << 9)
438 #define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)
439 #define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))
440 #define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)
441 #define BRIDGE_CTRL_WIDGET_ID_MASK	(BRIDGE_CTRL_WIDGET_ID(0xf))
442 
443 /* Bridge Response buffer Error Upper Register bit fields definition */
444 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
445 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
446 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
447 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
448 #define BRIDGE_RESP_ERRRUPPR_BUFMASK	(0xFFFF)
449 
450 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x)	\
451 			(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
452 				BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
453 
454 #define BRIDGE_RESP_ERRUPPR_DEVICE(x)	\
455 			(((x) &	 BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
456 				 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
457 
458 /* Bridge direct mapping register bits definition */
459 #define BRIDGE_DIRMAP_W_ID_SHFT		20
460 #define BRIDGE_DIRMAP_W_ID		(0xf << BRIDGE_DIRMAP_W_ID_SHFT)
461 #define BRIDGE_DIRMAP_RMF_64		(0x1 << 18)
462 #define BRIDGE_DIRMAP_ADD512		(0x1 << 17)
463 #define BRIDGE_DIRMAP_OFF		(0x1ffff << 0)
464 #define BRIDGE_DIRMAP_OFF_ADDRSHFT	(31)	/* lsbit of DIRMAP_OFF is xtalk address bit 31 */
465 
466 /* Bridge Arbitration register bits definition */
467 #define BRIDGE_ARB_REQ_WAIT_TICK(x)	((x) << 16)
468 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK	BRIDGE_ARB_REQ_WAIT_TICK(0x3)
469 #define BRIDGE_ARB_REQ_WAIT_EN(x)	((x) << 8)
470 #define BRIDGE_ARB_REQ_WAIT_EN_MASK	BRIDGE_ARB_REQ_WAIT_EN(0xff)
471 #define BRIDGE_ARB_FREEZE_GNT		(1 << 6)
472 #define BRIDGE_ARB_HPRI_RING_B2		(1 << 5)
473 #define BRIDGE_ARB_HPRI_RING_B1		(1 << 4)
474 #define BRIDGE_ARB_HPRI_RING_B0		(1 << 3)
475 #define BRIDGE_ARB_LPRI_RING_B2		(1 << 2)
476 #define BRIDGE_ARB_LPRI_RING_B1		(1 << 1)
477 #define BRIDGE_ARB_LPRI_RING_B0		(1 << 0)
478 
479 /* Bridge Bus time-out register bits definition */
480 #define BRIDGE_BUS_PCI_RETRY_HLD(x)	((x) << 16)
481 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK	BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
482 #define BRIDGE_BUS_GIO_TIMEOUT		(1 << 12)
483 #define BRIDGE_BUS_PCI_RETRY_CNT(x)	((x) << 0)
484 #define BRIDGE_BUS_PCI_RETRY_MASK	BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
485 
486 /* Bridge interrupt status register bits definition */
487 #define BRIDGE_ISR_MULTI_ERR		(0x1u << 31)
488 #define BRIDGE_ISR_PMU_ESIZE_FAULT	(0x1 << 30)
489 #define BRIDGE_ISR_UNEXP_RESP		(0x1 << 29)
490 #define BRIDGE_ISR_BAD_XRESP_PKT	(0x1 << 28)
491 #define BRIDGE_ISR_BAD_XREQ_PKT		(0x1 << 27)
492 #define BRIDGE_ISR_RESP_XTLK_ERR	(0x1 << 26)
493 #define BRIDGE_ISR_REQ_XTLK_ERR		(0x1 << 25)
494 #define BRIDGE_ISR_INVLD_ADDR		(0x1 << 24)
495 #define BRIDGE_ISR_UNSUPPORTED_XOP	(0x1 << 23)
496 #define BRIDGE_ISR_XREQ_FIFO_OFLOW	(0x1 << 22)
497 #define BRIDGE_ISR_LLP_REC_SNERR	(0x1 << 21)
498 #define BRIDGE_ISR_LLP_REC_CBERR	(0x1 << 20)
499 #define BRIDGE_ISR_LLP_RCTY		(0x1 << 19)
500 #define BRIDGE_ISR_LLP_TX_RETRY		(0x1 << 18)
501 #define BRIDGE_ISR_LLP_TCTY		(0x1 << 17)
502 #define BRIDGE_ISR_SSRAM_PERR		(0x1 << 16)
503 #define BRIDGE_ISR_PCI_ABORT		(0x1 << 15)
504 #define BRIDGE_ISR_PCI_PARITY		(0x1 << 14)
505 #define BRIDGE_ISR_PCI_SERR		(0x1 << 13)
506 #define BRIDGE_ISR_PCI_PERR		(0x1 << 12)
507 #define BRIDGE_ISR_PCI_MST_TIMEOUT	(0x1 << 11)
508 #define BRIDGE_ISR_GIO_MST_TIMEOUT	BRIDGE_ISR_PCI_MST_TIMEOUT
509 #define BRIDGE_ISR_PCI_RETRY_CNT	(0x1 << 10)
510 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT	(0x1 << 9)
511 #define BRIDGE_ISR_GIO_B_ENBL_ERR	(0x1 << 8)
512 #define BRIDGE_ISR_INT_MSK		(0xff << 0)
513 #define BRIDGE_ISR_INT(x)		(0x1 << (x))
514 
515 #define BRIDGE_ISR_LINK_ERROR		\
516 		(BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|	\
517 		 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|		\
518 		 BRIDGE_ISR_LLP_TCTY)
519 
520 #define BRIDGE_ISR_PCIBUS_PIOERR	\
521 		(BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
522 
523 #define BRIDGE_ISR_PCIBUS_ERROR		\
524 		(BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|		\
525 		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|		\
526 		 BRIDGE_ISR_PCI_PARITY)
527 
528 #define BRIDGE_ISR_XTALK_ERROR		\
529 		(BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
530 		 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|	\
531 		 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|	\
532 		 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|	\
533 		 BRIDGE_ISR_UNEXP_RESP)
534 
535 #define BRIDGE_ISR_ERRORS		\
536 		(BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|		\
537 		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|		\
538 		 BRIDGE_ISR_PMU_ESIZE_FAULT)
539 
540 /*
541  * List of Errors which are fatal and kill the system
542  */
543 #define BRIDGE_ISR_ERROR_FATAL		\
544 		((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
545 		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
546 
547 #define BRIDGE_ISR_ERROR_DUMP		\
548 		(BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|	\
549 		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
550 
551 /* Bridge interrupt enable register bits definition */
552 #define BRIDGE_IMR_UNEXP_RESP		BRIDGE_ISR_UNEXP_RESP
553 #define BRIDGE_IMR_PMU_ESIZE_FAULT	BRIDGE_ISR_PMU_ESIZE_FAULT
554 #define BRIDGE_IMR_BAD_XRESP_PKT	BRIDGE_ISR_BAD_XRESP_PKT
555 #define BRIDGE_IMR_BAD_XREQ_PKT		BRIDGE_ISR_BAD_XREQ_PKT
556 #define BRIDGE_IMR_RESP_XTLK_ERR	BRIDGE_ISR_RESP_XTLK_ERR
557 #define BRIDGE_IMR_REQ_XTLK_ERR		BRIDGE_ISR_REQ_XTLK_ERR
558 #define BRIDGE_IMR_INVLD_ADDR		BRIDGE_ISR_INVLD_ADDR
559 #define BRIDGE_IMR_UNSUPPORTED_XOP	BRIDGE_ISR_UNSUPPORTED_XOP
560 #define BRIDGE_IMR_XREQ_FIFO_OFLOW	BRIDGE_ISR_XREQ_FIFO_OFLOW
561 #define BRIDGE_IMR_LLP_REC_SNERR	BRIDGE_ISR_LLP_REC_SNERR
562 #define BRIDGE_IMR_LLP_REC_CBERR	BRIDGE_ISR_LLP_REC_CBERR
563 #define BRIDGE_IMR_LLP_RCTY		BRIDGE_ISR_LLP_RCTY
564 #define BRIDGE_IMR_LLP_TX_RETRY		BRIDGE_ISR_LLP_TX_RETRY
565 #define BRIDGE_IMR_LLP_TCTY		BRIDGE_ISR_LLP_TCTY
566 #define BRIDGE_IMR_SSRAM_PERR		BRIDGE_ISR_SSRAM_PERR
567 #define BRIDGE_IMR_PCI_ABORT		BRIDGE_ISR_PCI_ABORT
568 #define BRIDGE_IMR_PCI_PARITY		BRIDGE_ISR_PCI_PARITY
569 #define BRIDGE_IMR_PCI_SERR		BRIDGE_ISR_PCI_SERR
570 #define BRIDGE_IMR_PCI_PERR		BRIDGE_ISR_PCI_PERR
571 #define BRIDGE_IMR_PCI_MST_TIMEOUT	BRIDGE_ISR_PCI_MST_TIMEOUT
572 #define BRIDGE_IMR_GIO_MST_TIMEOUT	BRIDGE_ISR_GIO_MST_TIMEOUT
573 #define BRIDGE_IMR_PCI_RETRY_CNT	BRIDGE_ISR_PCI_RETRY_CNT
574 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT	BRIDGE_ISR_XREAD_REQ_TIMEOUT
575 #define BRIDGE_IMR_GIO_B_ENBL_ERR	BRIDGE_ISR_GIO_B_ENBL_ERR
576 #define BRIDGE_IMR_INT_MSK		BRIDGE_ISR_INT_MSK
577 #define BRIDGE_IMR_INT(x)		BRIDGE_ISR_INT(x)
578 
579 /* Bridge interrupt reset register bits definition */
580 #define BRIDGE_IRR_MULTI_CLR		(0x1 << 6)
581 #define BRIDGE_IRR_CRP_GRP_CLR		(0x1 << 5)
582 #define BRIDGE_IRR_RESP_BUF_GRP_CLR	(0x1 << 4)
583 #define BRIDGE_IRR_REQ_DSP_GRP_CLR	(0x1 << 3)
584 #define BRIDGE_IRR_LLP_GRP_CLR		(0x1 << 2)
585 #define BRIDGE_IRR_SSRAM_GRP_CLR	(0x1 << 1)
586 #define BRIDGE_IRR_PCI_GRP_CLR		(0x1 << 0)
587 #define BRIDGE_IRR_GIO_GRP_CLR		(0x1 << 0)
588 #define BRIDGE_IRR_ALL_CLR		0x7f
589 
590 #define BRIDGE_IRR_CRP_GRP		(BRIDGE_ISR_UNEXP_RESP | \
591 					 BRIDGE_ISR_XREQ_FIFO_OFLOW)
592 #define BRIDGE_IRR_RESP_BUF_GRP		(BRIDGE_ISR_BAD_XRESP_PKT | \
593 					 BRIDGE_ISR_RESP_XTLK_ERR | \
594 					 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
595 #define BRIDGE_IRR_REQ_DSP_GRP		(BRIDGE_ISR_UNSUPPORTED_XOP | \
596 					 BRIDGE_ISR_BAD_XREQ_PKT | \
597 					 BRIDGE_ISR_REQ_XTLK_ERR | \
598 					 BRIDGE_ISR_INVLD_ADDR)
599 #define BRIDGE_IRR_LLP_GRP		(BRIDGE_ISR_LLP_REC_SNERR | \
600 					 BRIDGE_ISR_LLP_REC_CBERR | \
601 					 BRIDGE_ISR_LLP_RCTY | \
602 					 BRIDGE_ISR_LLP_TX_RETRY | \
603 					 BRIDGE_ISR_LLP_TCTY)
604 #define BRIDGE_IRR_SSRAM_GRP		(BRIDGE_ISR_SSRAM_PERR | \
605 					 BRIDGE_ISR_PMU_ESIZE_FAULT)
606 #define BRIDGE_IRR_PCI_GRP		(BRIDGE_ISR_PCI_ABORT | \
607 					 BRIDGE_ISR_PCI_PARITY | \
608 					 BRIDGE_ISR_PCI_SERR | \
609 					 BRIDGE_ISR_PCI_PERR | \
610 					 BRIDGE_ISR_PCI_MST_TIMEOUT | \
611 					 BRIDGE_ISR_PCI_RETRY_CNT)
612 
613 #define BRIDGE_IRR_GIO_GRP		(BRIDGE_ISR_GIO_B_ENBL_ERR | \
614 					 BRIDGE_ISR_GIO_MST_TIMEOUT)
615 
616 /* Bridge INT_DEV register bits definition */
617 #define BRIDGE_INT_DEV_SHFT(n)		((n)*3)
618 #define BRIDGE_INT_DEV_MASK(n)		(0x7 << BRIDGE_INT_DEV_SHFT(n))
619 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
620 
621 /* Bridge interrupt(x) register bits definition */
622 #define BRIDGE_INT_ADDR_HOST		0x0003FF00
623 #define BRIDGE_INT_ADDR_FLD		0x000000FF
624 
625 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK	0x1f0000
626 #define BRIDGE_TMO_GIO_TIMEOUT_MASK	0x001000
627 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK	0x0003ff
628 
629 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX	0x3ff
630 
631 /*
632  * The NASID should be shifted by this amount and stored into the
633  * interrupt(x) register.
634  */
635 #define BRIDGE_INT_ADDR_NASID_SHFT	8
636 
637 /*
638  * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
639  * memory.
640  */
641 #define BRIDGE_INT_ADDR_DEST_IO		(1 << 17)
642 #define BRIDGE_INT_ADDR_DEST_MEM	0
643 #define BRIDGE_INT_ADDR_MASK		(1 << 17)
644 
645 /* Bridge device(x) register bits definition */
646 #define BRIDGE_DEV_ERR_LOCK_EN		0x10000000
647 #define BRIDGE_DEV_PAGE_CHK_DIS		0x08000000
648 #define BRIDGE_DEV_FORCE_PCI_PAR	0x04000000
649 #define BRIDGE_DEV_VIRTUAL_EN		0x02000000
650 #define BRIDGE_DEV_PMU_WRGA_EN		0x01000000
651 #define BRIDGE_DEV_DIR_WRGA_EN		0x00800000
652 #define BRIDGE_DEV_DEV_SIZE		0x00400000
653 #define BRIDGE_DEV_RT			0x00200000
654 #define BRIDGE_DEV_SWAP_PMU		0x00100000
655 #define BRIDGE_DEV_SWAP_DIR		0x00080000
656 #define BRIDGE_DEV_PREF			0x00040000
657 #define BRIDGE_DEV_PRECISE		0x00020000
658 #define BRIDGE_DEV_COH			0x00010000
659 #define BRIDGE_DEV_BARRIER		0x00008000
660 #define BRIDGE_DEV_GBR			0x00004000
661 #define BRIDGE_DEV_DEV_SWAP		0x00002000
662 #define BRIDGE_DEV_DEV_IO_MEM		0x00001000
663 #define BRIDGE_DEV_OFF_MASK		0x00000fff
664 #define BRIDGE_DEV_OFF_ADDR_SHFT	20
665 
666 #define BRIDGE_DEV_PMU_BITS		(BRIDGE_DEV_PMU_WRGA_EN		| \
667 					 BRIDGE_DEV_SWAP_PMU)
668 #define BRIDGE_DEV_D32_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
669 					 BRIDGE_DEV_SWAP_DIR		| \
670 					 BRIDGE_DEV_PREF		| \
671 					 BRIDGE_DEV_PRECISE		| \
672 					 BRIDGE_DEV_COH			| \
673 					 BRIDGE_DEV_BARRIER)
674 #define BRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
675 					 BRIDGE_DEV_SWAP_DIR		| \
676 					 BRIDGE_DEV_COH			| \
677 					 BRIDGE_DEV_BARRIER)
678 
679 /* Bridge Error Upper register bit field definition */
680 #define BRIDGE_ERRUPPR_DEVMASTER	(0x1 << 20)	/* Device was master */
681 #define BRIDGE_ERRUPPR_PCIVDEV		(0x1 << 19)	/* Virtual Req value */
682 #define BRIDGE_ERRUPPR_DEVNUM_SHFT	(16)
683 #define BRIDGE_ERRUPPR_DEVNUM_MASK	(0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
684 #define BRIDGE_ERRUPPR_DEVICE(err)	(((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
685 #define BRIDGE_ERRUPPR_ADDRMASK		(0xFFFF)
686 
687 /* Bridge interrupt mode register bits definition */
688 #define BRIDGE_INTMODE_CLR_PKT_EN(x)	(0x1 << (x))
689 
690 /* this should be written to the xbow's link_control(x) register */
691 #define BRIDGE_CREDIT	3
692 
693 /* RRB assignment register */
694 #define BRIDGE_RRB_EN	0x8	/* after shifting down */
695 #define BRIDGE_RRB_DEV	0x7	/* after shifting down */
696 #define BRIDGE_RRB_VDEV 0x4	/* after shifting down */
697 #define BRIDGE_RRB_PDEV 0x3	/* after shifting down */
698 
699 /* RRB status register */
700 #define BRIDGE_RRB_VALID(r)	(0x00010000<<(r))
701 #define BRIDGE_RRB_INUSE(r)	(0x00000001<<(r))
702 
703 /* RRB clear register */
704 #define BRIDGE_RRB_CLEAR(r)	(0x00000001<<(r))
705 
706 /* xbox system controller declarations */
707 #define XBOX_BRIDGE_WID		8
708 #define FLASH_PROM1_BASE	0xE00000 /* To read the xbox sysctlr status */
709 #define XBOX_RPS_EXISTS		1 << 6	 /* RPS bit in status register */
710 #define XBOX_RPS_FAIL		1 << 4	 /* RPS status bit in register */
711 
712 /* ========================================================================
713  */
714 /*
715  * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
716  * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
717  */
718 /* XTALK addresses that map into Bridge Bus addr space */
719 #define BRIDGE_PIO32_XTALK_ALIAS_BASE	0x000040000000L
720 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT	0x00007FFFFFFFL
721 #define BRIDGE_PIO64_XTALK_ALIAS_BASE	0x000080000000L
722 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT	0x0000BFFFFFFFL
723 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE	0x000100000000L
724 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT	0x0001FFFFFFFFL
725 
726 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
727 #define BRIDGE_MIN_PIO_ADDR_MEM		0x00000000	/* 1G PCI memory space */
728 #define BRIDGE_MAX_PIO_ADDR_MEM		0x3fffffff
729 #define BRIDGE_MIN_PIO_ADDR_IO		0x00000000	/* 4G PCI IO space */
730 #define BRIDGE_MAX_PIO_ADDR_IO		0xffffffff
731 
732 /* XTALK addresses that map into PCI addresses */
733 #define BRIDGE_PCI_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
734 #define BRIDGE_PCI_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
735 #define BRIDGE_PCI_MEM64_BASE		BRIDGE_PIO64_XTALK_ALIAS_BASE
736 #define BRIDGE_PCI_MEM64_LIMIT		BRIDGE_PIO64_XTALK_ALIAS_LIMIT
737 #define BRIDGE_PCI_IO_BASE		BRIDGE_PCIIO_XTALK_ALIAS_BASE
738 #define BRIDGE_PCI_IO_LIMIT		BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
739 
740 /*
741  * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
742  */
743 /* Bridge Bus DMA addresses */
744 #define BRIDGE_LOCAL_BASE		0
745 #define BRIDGE_DMA_MAPPED_BASE		0x40000000
746 #define BRIDGE_DMA_MAPPED_SIZE		0x40000000	/* 1G Bytes */
747 #define BRIDGE_DMA_DIRECT_BASE		0x80000000
748 #define BRIDGE_DMA_DIRECT_SIZE		0x80000000	/* 2G Bytes */
749 
750 #define PCI32_LOCAL_BASE		BRIDGE_LOCAL_BASE
751 
752 /* PCI addresses of regions decoded by Bridge for DMA */
753 #define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
754 #define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE
755 
756 #define IS_PCI32_LOCAL(x)	((ulong_t)(x) < PCI32_MAPPED_BASE)
757 #define IS_PCI32_MAPPED(x)	((ulong_t)(x) < PCI32_DIRECT_BASE && \
758 					(ulong_t)(x) >= PCI32_MAPPED_BASE)
759 #define IS_PCI32_DIRECT(x)	((ulong_t)(x) >= PCI32_MAPPED_BASE)
760 #define IS_PCI64(x)		((ulong_t)(x) >= PCI64_BASE)
761 
762 /*
763  * The GIO address space.
764  */
765 /* Xtalk to GIO PIO */
766 #define BRIDGE_GIO_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
767 #define BRIDGE_GIO_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
768 
769 #define GIO_LOCAL_BASE			BRIDGE_LOCAL_BASE
770 
771 /* GIO addresses of regions decoded by Bridge for DMA */
772 #define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
773 #define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE
774 
775 #define IS_GIO_LOCAL(x)		((ulong_t)(x) < GIO_MAPPED_BASE)
776 #define IS_GIO_MAPPED(x)	((ulong_t)(x) < GIO_DIRECT_BASE && \
777 					(ulong_t)(x) >= GIO_MAPPED_BASE)
778 #define IS_GIO_DIRECT(x)	((ulong_t)(x) >= GIO_MAPPED_BASE)
779 
780 /* PCI to xtalk mapping */
781 
782 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
783  * which xtalk address is accessed
784  */
785 #define BRIDGE_DIRECT_32_SEG_SIZE	BRIDGE_DMA_DIRECT_SIZE
786 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)		\
787 	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +	\
788 		((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
789 
790 /* 64-bit address attribute masks */
791 #define PCI64_ATTR_TARG_MASK	0xf000000000000000
792 #define PCI64_ATTR_TARG_SHFT	60
793 #define PCI64_ATTR_PREF		0x0800000000000000
794 #define PCI64_ATTR_PREC		0x0400000000000000
795 #define PCI64_ATTR_VIRTUAL	0x0200000000000000
796 #define PCI64_ATTR_BAR		0x0100000000000000
797 #define PCI64_ATTR_RMF_MASK	0x00ff000000000000
798 #define PCI64_ATTR_RMF_SHFT	48
799 
800 #ifndef __ASSEMBLY__
801 /* Address translation entry for mapped pci32 accesses */
802 typedef union ate_u {
803 	u64	ent;
804 	struct ate_s {
805 		u64	rmf:16;
806 		u64	addr:36;
807 		u64	targ:4;
808 		u64	reserved:3;
809 		u64	barrier:1;
810 		u64	prefetch:1;
811 		u64	precise:1;
812 		u64	coherent:1;
813 		u64	valid:1;
814 	} field;
815 } ate_t;
816 #endif /* !__ASSEMBLY__ */
817 
818 #define ATE_V		0x01
819 #define ATE_CO		0x02
820 #define ATE_PREC	0x04
821 #define ATE_PREF	0x08
822 #define ATE_BAR		0x10
823 
824 #define ATE_PFNSHIFT		12
825 #define ATE_TIDSHIFT		8
826 #define ATE_RMFSHIFT		48
827 
828 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
829 				((xid)<<ATE_TIDSHIFT) | \
830 				(attr)
831 
832 #define BRIDGE_INTERNAL_ATES	128
833 
834 struct bridge_controller {
835 	struct pci_controller	pc;
836 	struct resource		mem;
837 	struct resource		io;
838 	struct resource		busn;
839 	bridge_t		*base;
840 	nasid_t			nasid;
841 	unsigned int		widget_id;
842 	unsigned int		irq_cpu;
843 	u64			baddr;
844 	unsigned int		pci_int[8];
845 };
846 
847 #define BRIDGE_CONTROLLER(bus) \
848 	((struct bridge_controller *)((bus)->sysdata))
849 
850 extern void register_bridge_irq(unsigned int irq);
851 extern int request_bridge_irq(struct bridge_controller *bc);
852 
853 extern struct pci_ops bridge_pci_ops;
854 
855 #endif /* _ASM_PCI_BRIDGE_H */
856