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Searched refs:Bytes (Results 1 – 6 of 6) sorted by relevance

/arch/metag/tbx/
Dtbistring.c51 if (!seg || seg->Bytes < sizeof(TBISTR)) in __TBIFindStr()
80 search = (const TBISTR *)((const char *)search + search->Bytes); in __TBIFindStr()
108 search = (const TBISTR *)((const char *)search + search->Bytes); in __TBITransStr()
/arch/metag/include/asm/
Dtbx.h717 unsigned int Bytes; /* Size of region in bytes */ member
768 short Bytes; /* Length of entry in Bytes */ member
936 PTBISEG __TBINewSeg( PTBISEG pFromSeg, int Id, unsigned int Bytes );
939 PTBISEG __TBIMakeNewSeg( int Id, unsigned int Bytes );
1159 void *__TBIPhysAccess( int Channel, int PhysAddr, int Bytes );
1371 int __TBIMMUCacheStride( const void *pStart, int Bytes );
1383 void __TBIMMUCacheFlush( const void *pStart, int Bytes, int SegType );
1404 void *__TBICoreCacheOpt( const void *pStart, int Bytes, int SegType, int Mode );
1405 void __TBICoreCacheEnd( const void *pOpt, int Bytes, int SegType );
1416 void __TBIPhysFlush( int Channel, const void *pStart, int Bytes );
/arch/metag/kernel/
Dsetup.c343 heap_end = (unsigned long)p_heap->pGAddr + p_heap->Bytes; in setup_arch()
345 heap_end = (unsigned long)p_heap->pLAddr + p_heap->Bytes; in setup_arch()
/arch/x86/crypto/sha-mb/
Dsha1_x8_avx2.S305 #align rsp to 32 Bytes
/arch/x86/crypto/
Daesni-intel_avx-x86_64.S1365 # output r13 Bytes
2640 # output r13 Bytes
/arch/arm/mm/
DKconfig1022 Setting ARM L1 cache line size to 64 Bytes.