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Searched refs:CACHE_LINE_SIZE (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mm/
Dcache-feroceon-l2.c137 #define CACHE_LINE_SIZE 32 macro
146 BUG_ON(start & (CACHE_LINE_SIZE - 1)); in calc_range_end()
147 BUG_ON(end & (CACHE_LINE_SIZE - 1)); in calc_range_end()
176 if (start & (CACHE_LINE_SIZE - 1)) { in feroceon_l2_inv_range()
177 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); in feroceon_l2_inv_range()
178 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in feroceon_l2_inv_range()
184 if (start < end && end & (CACHE_LINE_SIZE - 1)) { in feroceon_l2_inv_range()
185 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); in feroceon_l2_inv_range()
186 end &= ~(CACHE_LINE_SIZE - 1); in feroceon_l2_inv_range()
194 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); in feroceon_l2_inv_range()
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Dcache-tauros2.c62 #define CACHE_LINE_SIZE 32 macro
69 if (start & (CACHE_LINE_SIZE - 1)) { in tauros2_inv_range()
70 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); in tauros2_inv_range()
71 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in tauros2_inv_range()
77 if (end & (CACHE_LINE_SIZE - 1)) { in tauros2_inv_range()
78 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); in tauros2_inv_range()
79 end &= ~(CACHE_LINE_SIZE - 1); in tauros2_inv_range()
87 start += CACHE_LINE_SIZE; in tauros2_inv_range()
95 start &= ~(CACHE_LINE_SIZE - 1); in tauros2_clean_range()
98 start += CACHE_LINE_SIZE; in tauros2_clean_range()
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Dcache-xsc3l2.c27 #define CACHE_LINE_SIZE 32 macro
112 if (start & (CACHE_LINE_SIZE - 1)) { in xsc3_l2_inv_range()
113 vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr); in xsc3_l2_inv_range()
116 start = (start | (CACHE_LINE_SIZE - 1)) + 1; in xsc3_l2_inv_range()
122 while (start < (end & ~(CACHE_LINE_SIZE - 1))) { in xsc3_l2_inv_range()
125 start += CACHE_LINE_SIZE; in xsc3_l2_inv_range()
148 start &= ~(CACHE_LINE_SIZE - 1); in xsc3_l2_clean_range()
152 start += CACHE_LINE_SIZE; in xsc3_l2_clean_range()
191 start &= ~(CACHE_LINE_SIZE - 1); in xsc3_l2_flush_range()
196 start += CACHE_LINE_SIZE; in xsc3_l2_flush_range()
Dcache-l2x0.c49 #define CACHE_LINE_SIZE 32 macro
188 start += CACHE_LINE_SIZE; in __l2c210_op_pa_range()
196 if (start & (CACHE_LINE_SIZE - 1)) { in l2c210_inv_range()
197 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_inv_range()
199 start += CACHE_LINE_SIZE; in l2c210_inv_range()
202 if (end & (CACHE_LINE_SIZE - 1)) { in l2c210_inv_range()
203 end &= ~(CACHE_LINE_SIZE - 1); in l2c210_inv_range()
215 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_clean_range()
224 start &= ~(CACHE_LINE_SIZE - 1); in l2c210_flush_range()
300 start += CACHE_LINE_SIZE; in l2c220_op_pa_range()
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Dcache-v6.S21 #define CACHE_LINE_SIZE 32 macro
135 bic r0, r0, #CACHE_LINE_SIZE - 1
138 add r0, r0, #CACHE_LINE_SIZE
/arch/m68k/coldfire/
Dcache.c40 : "i" (CACHE_LINE_SIZE), in mcf_cache_push()
/arch/m68k/include/asm/
Dm53xxacr.h64 #define CACHE_LINE_SIZE 16 /* 16 byte line size */ macro
Dm54xxacr.h64 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ macro