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Searched refs:CGU0_CTL (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf609/
Dclock.c142 u32 ctl = bfin_read32(CGU0_CTL); in pll_get_rate()
170 clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, in pll_set_rate()
189 u32 ctl = bfin_read32(CGU0_CTL); in sys_clk_get_rate()
219 u32 ctl = bfin_read32(CGU0_CTL); in sys_clk_round_rate()
/arch/blackfin/include/asm/
Dmem_init.h452 if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) in init_cgu()
455 bfin_write32(CGU0_CTL, cgu_ctl); in init_cgu()
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h3205 #define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */ macro