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1 #ifndef __ALPHA_CIA__H__
2 #define __ALPHA_CIA__H__
3 
4 /* Define to experiment with fitting everything into one 512MB HAE window.  */
5 #define CIA_ONE_HAE_WINDOW 1
6 
7 #include <linux/types.h>
8 #include <asm/compiler.h>
9 
10 /*
11  * CIA is the internal name for the 21171 chipset which provides
12  * memory controller and PCI access for the 21164 chip based systems.
13  * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
14  *
15  * The lineage is a bit confused, since the 21174 was reportedly started
16  * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
17  * in 21171 Pass 2 and 21172, but it also contains additional features.
18  *
19  * This file is based on:
20  *
21  * DECchip 21171 Core Logic Chipset
22  * Technical Reference Manual
23  *
24  * EC-QE18B-TE
25  *
26  * david.rusling@reo.mts.dec.com Initial Version.
27  *
28  */
29 
30 /*
31  * CIA ADDRESS BIT DEFINITIONS
32  *
33  *  3333 3333 3322 2222 2222 1111 1111 11
34  *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
35  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
36  *  1                                             000
37  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
38  *  |                                             |\|
39  *  |                               Byte Enable --+ |
40  *  |                             Transfer Length --+
41  *  +-- IO space, not cached
42  *
43  *   Byte      Transfer
44  *   Enable    Length    Transfer  Byte    Address
45  *   adr<6:5>  adr<4:3>  Length    Enable  Adder
46  *   ---------------------------------------------
47  *      00        00      Byte      1110   0x000
48  *      01        00      Byte      1101   0x020
49  *      10        00      Byte      1011   0x040
50  *      11        00      Byte      0111   0x060
51  *
52  *      00        01      Word      1100   0x008
53  *      01        01      Word      1001   0x028 <= Not supported in this code.
54  *      10        01      Word      0011   0x048
55  *
56  *      00        10      Tribyte   1000   0x010
57  *      01        10      Tribyte   0001   0x030
58  *
59  *      10        11      Longword  0000   0x058
60  *
61  *      Note that byte enables are asserted low.
62  *
63  */
64 
65 #define CIA_MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
66 #define CIA_MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
67 #define CIA_MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
68 
69 /*
70  * 21171-CA Control and Status Registers
71  */
72 #define CIA_IOC_CIA_REV			(IDENT_ADDR + 0x8740000080UL)
73 #  define CIA_REV_MASK			0xff
74 #define CIA_IOC_PCI_LAT			(IDENT_ADDR + 0x87400000C0UL)
75 #define CIA_IOC_CIA_CTRL		(IDENT_ADDR + 0x8740000100UL)
76 #  define CIA_CTRL_PCI_EN		(1 << 0)
77 #  define CIA_CTRL_PCI_LOCK_EN		(1 << 1)
78 #  define CIA_CTRL_PCI_LOOP_EN		(1 << 2)
79 #  define CIA_CTRL_FST_BB_EN		(1 << 3)
80 #  define CIA_CTRL_PCI_MST_EN		(1 << 4)
81 #  define CIA_CTRL_PCI_MEM_EN		(1 << 5)
82 #  define CIA_CTRL_PCI_REQ64_EN		(1 << 6)
83 #  define CIA_CTRL_PCI_ACK64_EN		(1 << 7)
84 #  define CIA_CTRL_ADDR_PE_EN		(1 << 8)
85 #  define CIA_CTRL_PERR_EN		(1 << 9)
86 #  define CIA_CTRL_FILL_ERR_EN		(1 << 10)
87 #  define CIA_CTRL_MCHK_ERR_EN		(1 << 11)
88 #  define CIA_CTRL_ECC_CHK_EN		(1 << 12)
89 #  define CIA_CTRL_ASSERT_IDLE_BC	(1 << 13)
90 #  define CIA_CTRL_COM_IDLE_BC		(1 << 14)
91 #  define CIA_CTRL_CSR_IOA_BYPASS	(1 << 15)
92 #  define CIA_CTRL_IO_FLUSHREQ_EN	(1 << 16)
93 #  define CIA_CTRL_CPU_FLUSHREQ_EN	(1 << 17)
94 #  define CIA_CTRL_ARB_CPU_EN		(1 << 18)
95 #  define CIA_CTRL_EN_ARB_LINK		(1 << 19)
96 #  define CIA_CTRL_RD_TYPE_SHIFT	20
97 #  define CIA_CTRL_RL_TYPE_SHIFT	24
98 #  define CIA_CTRL_RM_TYPE_SHIFT	28
99 #  define CIA_CTRL_EN_DMA_RD_PERF	(1 << 31)
100 #define CIA_IOC_CIA_CNFG		(IDENT_ADDR + 0x8740000140UL)
101 #  define CIA_CNFG_IOA_BWEN		(1 << 0)
102 #  define CIA_CNFG_PCI_MWEN		(1 << 4)
103 #  define CIA_CNFG_PCI_DWEN		(1 << 5)
104 #  define CIA_CNFG_PCI_WLEN		(1 << 8)
105 #define CIA_IOC_FLASH_CTRL		(IDENT_ADDR + 0x8740000200UL)
106 #define CIA_IOC_HAE_MEM			(IDENT_ADDR + 0x8740000400UL)
107 #define CIA_IOC_HAE_IO			(IDENT_ADDR + 0x8740000440UL)
108 #define CIA_IOC_CFG			(IDENT_ADDR + 0x8740000480UL)
109 #define CIA_IOC_CACK_EN			(IDENT_ADDR + 0x8740000600UL)
110 #  define CIA_CACK_EN_LOCK_EN		(1 << 0)
111 #  define CIA_CACK_EN_MB_EN		(1 << 1)
112 #  define CIA_CACK_EN_SET_DIRTY_EN	(1 << 2)
113 #  define CIA_CACK_EN_BC_VICTIM_EN	(1 << 3)
114 
115 
116 /*
117  * 21171-CA Diagnostic Registers
118  */
119 #define CIA_IOC_CIA_DIAG		(IDENT_ADDR + 0x8740002000UL)
120 #define CIA_IOC_DIAG_CHECK		(IDENT_ADDR + 0x8740003000UL)
121 
122 /*
123  * 21171-CA Performance Monitor registers
124  */
125 #define CIA_IOC_PERF_MONITOR		(IDENT_ADDR + 0x8740004000UL)
126 #define CIA_IOC_PERF_CONTROL		(IDENT_ADDR + 0x8740004040UL)
127 
128 /*
129  * 21171-CA Error registers
130  */
131 #define CIA_IOC_CPU_ERR0		(IDENT_ADDR + 0x8740008000UL)
132 #define CIA_IOC_CPU_ERR1		(IDENT_ADDR + 0x8740008040UL)
133 #define CIA_IOC_CIA_ERR			(IDENT_ADDR + 0x8740008200UL)
134 #  define CIA_ERR_COR_ERR		(1 << 0)
135 #  define CIA_ERR_UN_COR_ERR		(1 << 1)
136 #  define CIA_ERR_CPU_PE		(1 << 2)
137 #  define CIA_ERR_MEM_NEM		(1 << 3)
138 #  define CIA_ERR_PCI_SERR		(1 << 4)
139 #  define CIA_ERR_PERR			(1 << 5)
140 #  define CIA_ERR_PCI_ADDR_PE		(1 << 6)
141 #  define CIA_ERR_RCVD_MAS_ABT		(1 << 7)
142 #  define CIA_ERR_RCVD_TAR_ABT		(1 << 8)
143 #  define CIA_ERR_PA_PTE_INV		(1 << 9)
144 #  define CIA_ERR_FROM_WRT_ERR		(1 << 10)
145 #  define CIA_ERR_IOA_TIMEOUT		(1 << 11)
146 #  define CIA_ERR_LOST_CORR_ERR		(1 << 16)
147 #  define CIA_ERR_LOST_UN_CORR_ERR	(1 << 17)
148 #  define CIA_ERR_LOST_CPU_PE		(1 << 18)
149 #  define CIA_ERR_LOST_MEM_NEM		(1 << 19)
150 #  define CIA_ERR_LOST_PERR		(1 << 21)
151 #  define CIA_ERR_LOST_PCI_ADDR_PE	(1 << 22)
152 #  define CIA_ERR_LOST_RCVD_MAS_ABT	(1 << 23)
153 #  define CIA_ERR_LOST_RCVD_TAR_ABT	(1 << 24)
154 #  define CIA_ERR_LOST_PA_PTE_INV	(1 << 25)
155 #  define CIA_ERR_LOST_FROM_WRT_ERR	(1 << 26)
156 #  define CIA_ERR_LOST_IOA_TIMEOUT	(1 << 27)
157 #  define CIA_ERR_VALID			(1 << 31)
158 #define CIA_IOC_CIA_STAT		(IDENT_ADDR + 0x8740008240UL)
159 #define CIA_IOC_ERR_MASK		(IDENT_ADDR + 0x8740008280UL)
160 #define CIA_IOC_CIA_SYN			(IDENT_ADDR + 0x8740008300UL)
161 #define CIA_IOC_MEM_ERR0		(IDENT_ADDR + 0x8740008400UL)
162 #define CIA_IOC_MEM_ERR1		(IDENT_ADDR + 0x8740008440UL)
163 #define CIA_IOC_PCI_ERR0		(IDENT_ADDR + 0x8740008800UL)
164 #define CIA_IOC_PCI_ERR1		(IDENT_ADDR + 0x8740008840UL)
165 #define CIA_IOC_PCI_ERR3		(IDENT_ADDR + 0x8740008880UL)
166 
167 /*
168  * 21171-CA System configuration registers
169  */
170 #define CIA_IOC_MCR			(IDENT_ADDR + 0x8750000000UL)
171 #define CIA_IOC_MBA0			(IDENT_ADDR + 0x8750000600UL)
172 #define CIA_IOC_MBA2			(IDENT_ADDR + 0x8750000680UL)
173 #define CIA_IOC_MBA4			(IDENT_ADDR + 0x8750000700UL)
174 #define CIA_IOC_MBA6			(IDENT_ADDR + 0x8750000780UL)
175 #define CIA_IOC_MBA8			(IDENT_ADDR + 0x8750000800UL)
176 #define CIA_IOC_MBAA			(IDENT_ADDR + 0x8750000880UL)
177 #define CIA_IOC_MBAC			(IDENT_ADDR + 0x8750000900UL)
178 #define CIA_IOC_MBAE			(IDENT_ADDR + 0x8750000980UL)
179 #define CIA_IOC_TMG0			(IDENT_ADDR + 0x8750000B00UL)
180 #define CIA_IOC_TMG1			(IDENT_ADDR + 0x8750000B40UL)
181 #define CIA_IOC_TMG2			(IDENT_ADDR + 0x8750000B80UL)
182 
183 /*
184  * 2117A-CA PCI Address and Scatter-Gather Registers.
185  */
186 #define CIA_IOC_PCI_TBIA		(IDENT_ADDR + 0x8760000100UL)
187 
188 #define CIA_IOC_PCI_W0_BASE		(IDENT_ADDR + 0x8760000400UL)
189 #define CIA_IOC_PCI_W0_MASK		(IDENT_ADDR + 0x8760000440UL)
190 #define CIA_IOC_PCI_T0_BASE		(IDENT_ADDR + 0x8760000480UL)
191 
192 #define CIA_IOC_PCI_W1_BASE		(IDENT_ADDR + 0x8760000500UL)
193 #define CIA_IOC_PCI_W1_MASK		(IDENT_ADDR + 0x8760000540UL)
194 #define CIA_IOC_PCI_T1_BASE		(IDENT_ADDR + 0x8760000580UL)
195 
196 #define CIA_IOC_PCI_W2_BASE		(IDENT_ADDR + 0x8760000600UL)
197 #define CIA_IOC_PCI_W2_MASK		(IDENT_ADDR + 0x8760000640UL)
198 #define CIA_IOC_PCI_T2_BASE		(IDENT_ADDR + 0x8760000680UL)
199 
200 #define CIA_IOC_PCI_W3_BASE		(IDENT_ADDR + 0x8760000700UL)
201 #define CIA_IOC_PCI_W3_MASK		(IDENT_ADDR + 0x8760000740UL)
202 #define CIA_IOC_PCI_T3_BASE		(IDENT_ADDR + 0x8760000780UL)
203 
204 #define CIA_IOC_PCI_Wn_BASE(N)	(IDENT_ADDR + 0x8760000400UL + (N)*0x100)
205 #define CIA_IOC_PCI_Wn_MASK(N)	(IDENT_ADDR + 0x8760000440UL + (N)*0x100)
206 #define CIA_IOC_PCI_Tn_BASE(N)	(IDENT_ADDR + 0x8760000480UL + (N)*0x100)
207 
208 #define CIA_IOC_PCI_W_DAC		(IDENT_ADDR + 0x87600007C0UL)
209 
210 /*
211  * 2117A-CA Address Translation Registers.
212  */
213 
214 /* 8 tag registers, the first 4 of which are lockable.  */
215 #define CIA_IOC_TB_TAGn(n) \
216 	(IDENT_ADDR + 0x8760000800UL + (n)*0x40)
217 
218 /* 4 page registers per tag register.  */
219 #define CIA_IOC_TBn_PAGEm(n,m) \
220 	(IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
221 
222 /*
223  * Memory spaces:
224  */
225 #define CIA_IACK_SC			(IDENT_ADDR + 0x8720000000UL)
226 #define CIA_CONF			(IDENT_ADDR + 0x8700000000UL)
227 #define CIA_IO				(IDENT_ADDR + 0x8580000000UL)
228 #define CIA_SPARSE_MEM			(IDENT_ADDR + 0x8000000000UL)
229 #define CIA_SPARSE_MEM_R2		(IDENT_ADDR + 0x8400000000UL)
230 #define CIA_SPARSE_MEM_R3		(IDENT_ADDR + 0x8500000000UL)
231 #define CIA_DENSE_MEM		        (IDENT_ADDR + 0x8600000000UL)
232 #define CIA_BW_MEM			(IDENT_ADDR + 0x8800000000UL)
233 #define CIA_BW_IO			(IDENT_ADDR + 0x8900000000UL)
234 #define CIA_BW_CFG_0			(IDENT_ADDR + 0x8a00000000UL)
235 #define CIA_BW_CFG_1			(IDENT_ADDR + 0x8b00000000UL)
236 
237 /*
238  * ALCOR's GRU ASIC registers
239  */
240 #define GRU_INT_REQ			(IDENT_ADDR + 0x8780000000UL)
241 #define GRU_INT_MASK			(IDENT_ADDR + 0x8780000040UL)
242 #define GRU_INT_EDGE			(IDENT_ADDR + 0x8780000080UL)
243 #define GRU_INT_HILO			(IDENT_ADDR + 0x87800000C0UL)
244 #define GRU_INT_CLEAR			(IDENT_ADDR + 0x8780000100UL)
245 
246 #define GRU_CACHE_CNFG			(IDENT_ADDR + 0x8780000200UL)
247 #define GRU_SCR				(IDENT_ADDR + 0x8780000300UL)
248 #define GRU_LED				(IDENT_ADDR + 0x8780000800UL)
249 #define GRU_RESET			(IDENT_ADDR + 0x8780000900UL)
250 
251 #define ALCOR_GRU_INT_REQ_BITS		0x800fffffUL
252 #define XLT_GRU_INT_REQ_BITS		0x80003fffUL
253 #define GRU_INT_REQ_BITS		(alpha_mv.sys.cia.gru_int_req_bits+0)
254 
255 /*
256  * PYXIS interrupt control registers
257  */
258 #define PYXIS_INT_REQ			(IDENT_ADDR + 0x87A0000000UL)
259 #define PYXIS_INT_MASK			(IDENT_ADDR + 0x87A0000040UL)
260 #define PYXIS_INT_HILO			(IDENT_ADDR + 0x87A00000C0UL)
261 #define PYXIS_INT_ROUTE			(IDENT_ADDR + 0x87A0000140UL)
262 #define PYXIS_GPO			(IDENT_ADDR + 0x87A0000180UL)
263 #define PYXIS_INT_CNFG			(IDENT_ADDR + 0x87A00001C0UL)
264 #define PYXIS_RT_COUNT			(IDENT_ADDR + 0x87A0000200UL)
265 #define PYXIS_INT_TIME			(IDENT_ADDR + 0x87A0000240UL)
266 #define PYXIS_IIC_CTRL			(IDENT_ADDR + 0x87A00002C0UL)
267 #define PYXIS_RESET			(IDENT_ADDR + 0x8780000900UL)
268 
269 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
270 #define PYXIS_DAC_OFFSET		(1UL << 40)
271 
272 /*
273  * Data structure for handling CIA machine checks.
274  */
275 
276 /* System-specific info.  */
277 struct el_CIA_sysdata_mcheck {
278 	unsigned long	cpu_err0;
279 	unsigned long	cpu_err1;
280 	unsigned long	cia_err;
281 	unsigned long	cia_stat;
282 	unsigned long	err_mask;
283 	unsigned long	cia_syn;
284 	unsigned long	mem_err0;
285 	unsigned long	mem_err1;
286 	unsigned long	pci_err0;
287 	unsigned long	pci_err1;
288 	unsigned long	pci_err2;
289 };
290 
291 
292 #ifdef __KERNEL__
293 
294 #ifndef __EXTERN_INLINE
295 /* Do not touch, this should *NOT* be static inline */
296 #define __EXTERN_INLINE extern inline
297 #define __IO_EXTERN_INLINE
298 #endif
299 
300 /*
301  * I/O functions:
302  *
303  * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
304  * series of processors uses a sparse address mapping scheme to
305  * get at PCI memory and I/O.
306  */
307 
308 /*
309  * Memory functions.  64-bit and 32-bit accesses are done through
310  * dense memory space, everything else through sparse space.
311  *
312  * For reading and writing 8 and 16 bit quantities we need to
313  * go through one of the three sparse address mapping regions
314  * and use the HAE_MEM CSR to provide some bits of the address.
315  * The following few routines use only sparse address region 1
316  * which gives 1Gbyte of accessible space which relates exactly
317  * to the amount of PCI memory mapping *into* system address space.
318  * See p 6-17 of the specification but it looks something like this:
319  *
320  * 21164 Address:
321  *
322  *          3         2         1
323  * 9876543210987654321098765432109876543210
324  * 1ZZZZ0.PCI.QW.Address............BBLL
325  *
326  * ZZ = SBZ
327  * BB = Byte offset
328  * LL = Transfer length
329  *
330  * PCI Address:
331  *
332  * 3         2         1
333  * 10987654321098765432109876543210
334  * HHH....PCI.QW.Address........ 00
335  *
336  * HHH = 31:29 HAE_MEM CSR
337  *
338  */
339 
340 #define vip	volatile int __force *
341 #define vuip	volatile unsigned int __force *
342 #define vulp	volatile unsigned long __force *
343 
cia_ioread8(void __iomem * xaddr)344 __EXTERN_INLINE unsigned int cia_ioread8(void __iomem *xaddr)
345 {
346 	unsigned long addr = (unsigned long) xaddr;
347 	unsigned long result, base_and_type;
348 
349 	if (addr >= CIA_DENSE_MEM)
350 		base_and_type = CIA_SPARSE_MEM + 0x00;
351 	else
352 		base_and_type = CIA_IO + 0x00;
353 
354 	/* We can use CIA_MEM_R1_MASK for io ports too, since it is large
355 	   enough to cover all io ports, and smaller than CIA_IO.  */
356 	addr &= CIA_MEM_R1_MASK;
357 	result = *(vip) ((addr << 5) + base_and_type);
358 	return __kernel_extbl(result, addr & 3);
359 }
360 
cia_iowrite8(u8 b,void __iomem * xaddr)361 __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
362 {
363 	unsigned long addr = (unsigned long) xaddr;
364 	unsigned long w, base_and_type;
365 
366 	if (addr >= CIA_DENSE_MEM)
367 		base_and_type = CIA_SPARSE_MEM + 0x00;
368 	else
369 		base_and_type = CIA_IO + 0x00;
370 
371 	addr &= CIA_MEM_R1_MASK;
372 	w = __kernel_insbl(b, addr & 3);
373 	*(vuip) ((addr << 5) + base_and_type) = w;
374 }
375 
cia_ioread16(void __iomem * xaddr)376 __EXTERN_INLINE unsigned int cia_ioread16(void __iomem *xaddr)
377 {
378 	unsigned long addr = (unsigned long) xaddr;
379 	unsigned long result, base_and_type;
380 
381 	if (addr >= CIA_DENSE_MEM)
382 		base_and_type = CIA_SPARSE_MEM + 0x08;
383 	else
384 		base_and_type = CIA_IO + 0x08;
385 
386 	addr &= CIA_MEM_R1_MASK;
387 	result = *(vip) ((addr << 5) + base_and_type);
388 	return __kernel_extwl(result, addr & 3);
389 }
390 
cia_iowrite16(u16 b,void __iomem * xaddr)391 __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
392 {
393 	unsigned long addr = (unsigned long) xaddr;
394 	unsigned long w, base_and_type;
395 
396 	if (addr >= CIA_DENSE_MEM)
397 		base_and_type = CIA_SPARSE_MEM + 0x08;
398 	else
399 		base_and_type = CIA_IO + 0x08;
400 
401 	addr &= CIA_MEM_R1_MASK;
402 	w = __kernel_inswl(b, addr & 3);
403 	*(vuip) ((addr << 5) + base_and_type) = w;
404 }
405 
cia_ioread32(void __iomem * xaddr)406 __EXTERN_INLINE unsigned int cia_ioread32(void __iomem *xaddr)
407 {
408 	unsigned long addr = (unsigned long) xaddr;
409 	if (addr < CIA_DENSE_MEM)
410 		addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
411 	return *(vuip)addr;
412 }
413 
cia_iowrite32(u32 b,void __iomem * xaddr)414 __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
415 {
416 	unsigned long addr = (unsigned long) xaddr;
417 	if (addr < CIA_DENSE_MEM)
418 		addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
419 	*(vuip)addr = b;
420 }
421 
cia_ioportmap(unsigned long addr)422 __EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
423 {
424 	return (void __iomem *)(addr + CIA_IO);
425 }
426 
cia_ioremap(unsigned long addr,unsigned long size)427 __EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
428 					  unsigned long size)
429 {
430 	return (void __iomem *)(addr + CIA_DENSE_MEM);
431 }
432 
cia_is_ioaddr(unsigned long addr)433 __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
434 {
435 	return addr >= IDENT_ADDR + 0x8000000000UL;
436 }
437 
cia_is_mmio(const volatile void __iomem * addr)438 __EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
439 {
440 	return (unsigned long)addr >= CIA_DENSE_MEM;
441 }
442 
cia_bwx_ioportmap(unsigned long addr)443 __EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
444 {
445 	return (void __iomem *)(addr + CIA_BW_IO);
446 }
447 
cia_bwx_ioremap(unsigned long addr,unsigned long size)448 __EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
449 					      unsigned long size)
450 {
451 	return (void __iomem *)(addr + CIA_BW_MEM);
452 }
453 
cia_bwx_is_ioaddr(unsigned long addr)454 __EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
455 {
456 	return addr >= IDENT_ADDR + 0x8000000000UL;
457 }
458 
cia_bwx_is_mmio(const volatile void __iomem * addr)459 __EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
460 {
461 	return (unsigned long)addr < CIA_BW_IO;
462 }
463 
464 #undef vip
465 #undef vuip
466 #undef vulp
467 
468 #undef __IO_PREFIX
469 #define __IO_PREFIX		cia
470 #define cia_trivial_rw_bw	2
471 #define cia_trivial_rw_lq	1
472 #define cia_trivial_io_bw	0
473 #define cia_trivial_io_lq	0
474 #define cia_trivial_iounmap	1
475 #include <asm/io_trivial.h>
476 
477 #undef __IO_PREFIX
478 #define __IO_PREFIX		cia_bwx
479 #define cia_bwx_trivial_rw_bw	1
480 #define cia_bwx_trivial_rw_lq	1
481 #define cia_bwx_trivial_io_bw	1
482 #define cia_bwx_trivial_io_lq	1
483 #define cia_bwx_trivial_iounmap	1
484 #include <asm/io_trivial.h>
485 
486 #undef __IO_PREFIX
487 #ifdef CONFIG_ALPHA_PYXIS
488 #define __IO_PREFIX		cia_bwx
489 #else
490 #define __IO_PREFIX		cia
491 #endif
492 
493 #ifdef __IO_EXTERN_INLINE
494 #undef __EXTERN_INLINE
495 #undef __IO_EXTERN_INLINE
496 #endif
497 
498 #endif /* __KERNEL__ */
499 
500 #endif /* __ALPHA_CIA__H__ */
501