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Searched refs:CLASS2_MAILBOX_THRESHOLD_INTR (Results 1 – 4 of 4) sorted by relevance

/arch/powerpc/platforms/cell/
Dspu_base.c362 CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR; in spu_irq_class_2()
391 if (stat & CLASS2_MAILBOX_THRESHOLD_INTR) in spu_irq_class_2()
/arch/powerpc/platforms/cell/spufs/
Dhw_ops.c87 CLASS2_MAILBOX_THRESHOLD_INTR); in spu_hw_mbox_stat_poll()
Dbacking_ops.c119 ~CLASS2_MAILBOX_THRESHOLD_INTR; in spu_backing_mbox_stat_poll()
/arch/powerpc/include/asm/
Dspu.h542 #define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L macro