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1 #ifndef _ASM_S390_PCI_CLP_H
2 #define _ASM_S390_PCI_CLP_H
3 
4 #include <asm/clp.h>
5 
6 /*
7  * Call Logical Processor - Command Codes
8  */
9 #define CLP_LIST_PCI		0x0002
10 #define CLP_QUERY_PCI_FN	0x0003
11 #define CLP_QUERY_PCI_FNGRP	0x0004
12 #define CLP_SET_PCI_FN		0x0005
13 
14 /* PCI function handle list entry */
15 struct clp_fh_list_entry {
16 	u16 device_id;
17 	u16 vendor_id;
18 	u32 config_state :  1;
19 	u32		 : 31;
20 	u32 fid;		/* PCI function id */
21 	u32 fh;			/* PCI function handle */
22 } __packed;
23 
24 #define CLP_RC_SETPCIFN_FH	0x0101	/* Invalid PCI fn handle */
25 #define CLP_RC_SETPCIFN_FHOP	0x0102	/* Fn handle not valid for op */
26 #define CLP_RC_SETPCIFN_DMAAS	0x0103	/* Invalid DMA addr space */
27 #define CLP_RC_SETPCIFN_RES	0x0104	/* Insufficient resources */
28 #define CLP_RC_SETPCIFN_ALRDY	0x0105	/* Fn already in requested state */
29 #define CLP_RC_SETPCIFN_ERR	0x0106	/* Fn in permanent error state */
30 #define CLP_RC_SETPCIFN_RECPND	0x0107	/* Error recovery pending */
31 #define CLP_RC_SETPCIFN_BUSY	0x0108	/* Fn busy */
32 #define CLP_RC_LISTPCI_BADRT	0x010a	/* Resume token not recognized */
33 #define CLP_RC_QUERYPCIFG_PFGID	0x010b	/* Unrecognized PFGID */
34 
35 /* request or response block header length */
36 #define LIST_PCI_HDR_LEN	32
37 
38 /* Number of function handles fitting in response block */
39 #define CLP_FH_LIST_NR_ENTRIES				\
40 	((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)		\
41 		/ sizeof(struct clp_fh_list_entry))
42 
43 #define CLP_SET_ENABLE_PCI_FN	0	/* Yes, 0 enables it */
44 #define CLP_SET_DISABLE_PCI_FN	1	/* Yes, 1 disables it */
45 
46 #define CLP_UTIL_STR_LEN	64
47 #define CLP_PFIP_NR_SEGMENTS	4
48 
49 /* List PCI functions request */
50 struct clp_req_list_pci {
51 	struct clp_req_hdr hdr;
52 	u32 fmt			:  4;	/* cmd request block format */
53 	u32			: 28;
54 	u64 reserved1;
55 	u64 resume_token;
56 	u64 reserved2;
57 } __packed;
58 
59 /* List PCI functions response */
60 struct clp_rsp_list_pci {
61 	struct clp_rsp_hdr hdr;
62 	u32 fmt			:  4;	/* cmd request block format */
63 	u32			: 28;
64 	u64 reserved1;
65 	u64 resume_token;
66 	u32 reserved2;
67 	u16 max_fn;
68 	u8 reserved3;
69 	u8 entry_size;
70 	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
71 } __packed;
72 
73 /* Query PCI function request */
74 struct clp_req_query_pci {
75 	struct clp_req_hdr hdr;
76 	u32 fmt			:  4;	/* cmd request block format */
77 	u32			: 28;
78 	u64 reserved1;
79 	u32 fh;				/* function handle */
80 	u32 reserved2;
81 	u64 reserved3;
82 } __packed;
83 
84 /* Query PCI function response */
85 struct clp_rsp_query_pci {
86 	struct clp_rsp_hdr hdr;
87 	u32 fmt			:  4;	/* cmd request block format */
88 	u32			: 28;
89 	u64			: 64;
90 	u16 vfn;			/* virtual fn number */
91 	u16			:  7;
92 	u16 util_str_avail	:  1;	/* utility string available? */
93 	u16 pfgid		:  8;	/* pci function group id */
94 	u32 fid;			/* pci function id */
95 	u8 bar_size[PCI_BAR_COUNT];
96 	u16 pchid;
97 	u32 bar[PCI_BAR_COUNT];
98 	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
99 	u32			: 24;
100 	u8 pft;				/* pci function type */
101 	u64 sdma;			/* start dma as */
102 	u64 edma;			/* end dma as */
103 	u32 reserved[11];
104 	u32 uid;			/* user defined id */
105 	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
106 } __packed;
107 
108 /* Query PCI function group request */
109 struct clp_req_query_pci_grp {
110 	struct clp_req_hdr hdr;
111 	u32 fmt			:  4;	/* cmd request block format */
112 	u32			: 28;
113 	u64 reserved1;
114 	u32			: 24;
115 	u32 pfgid		:  8;	/* function group id */
116 	u32 reserved2;
117 	u64 reserved3;
118 } __packed;
119 
120 /* Query PCI function group response */
121 struct clp_rsp_query_pci_grp {
122 	struct clp_rsp_hdr hdr;
123 	u32 fmt			:  4;	/* cmd request block format */
124 	u32			: 28;
125 	u64 reserved1;
126 	u16			:  4;
127 	u16 noi			: 12;	/* number of interrupts */
128 	u8 version;
129 	u8			:  6;
130 	u8 frame		:  1;
131 	u8 refresh		:  1;	/* TLB refresh mode */
132 	u16 reserved2;
133 	u16 mui;
134 	u64 reserved3;
135 	u64 dasm;			/* dma address space mask */
136 	u64 msia;			/* MSI address */
137 	u64 reserved4;
138 	u64 reserved5;
139 } __packed;
140 
141 /* Set PCI function request */
142 struct clp_req_set_pci {
143 	struct clp_req_hdr hdr;
144 	u32 fmt			:  4;	/* cmd request block format */
145 	u32			: 28;
146 	u64 reserved1;
147 	u32 fh;				/* function handle */
148 	u16 reserved2;
149 	u8 oc;				/* operation controls */
150 	u8 ndas;			/* number of dma spaces */
151 	u64 reserved3;
152 } __packed;
153 
154 /* Set PCI function response */
155 struct clp_rsp_set_pci {
156 	struct clp_rsp_hdr hdr;
157 	u32 fmt			:  4;	/* cmd request block format */
158 	u32			: 28;
159 	u64 reserved1;
160 	u32 fh;				/* function handle */
161 	u32 reserved3;
162 	u64 reserved4;
163 } __packed;
164 
165 /* Combined request/response block structures used by clp insn */
166 struct clp_req_rsp_list_pci {
167 	struct clp_req_list_pci request;
168 	struct clp_rsp_list_pci response;
169 } __packed;
170 
171 struct clp_req_rsp_set_pci {
172 	struct clp_req_set_pci request;
173 	struct clp_rsp_set_pci response;
174 } __packed;
175 
176 struct clp_req_rsp_query_pci {
177 	struct clp_req_query_pci request;
178 	struct clp_rsp_query_pci response;
179 } __packed;
180 
181 struct clp_req_rsp_query_pci_grp {
182 	struct clp_req_query_pci_grp request;
183 	struct clp_rsp_query_pci_grp response;
184 } __packed;
185 
186 #endif
187