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Searched refs:CNS3XXX_PCIE0_HOST_BASE (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-cns3xxx/
Dpcie.c157 .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
Dcore.c53 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
Dcns3xxx.h167 #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ macro