Searched refs:CPLB_L1_CHBL (Results 1 – 4 of 4) sorted by relevance
12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)26 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)53 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)95 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT96 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY103 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
638 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable macro
111 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in dcplb_miss()144 d_data |= CPLB_L1_CHBL; in dcplb_miss()214 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in icplb_miss()245 i_data |= CPLB_L1_CHBL; in icplb_miss()362 d_data |= CPLB_L1_CHBL; in set_mask_dcplbs()
32 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; in generate_cplb_tables_cpu()36 d_cache = CPLB_L1_CHBL; in generate_cplb_tables_cpu()