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Searched refs:CPLB_PORTPRIO (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/kernel/cplb-mpu/
Dcplbinit.c54 i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()
Dcplbmgr.c205 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; in icplb_miss()
/arch/blackfin/include/asm/
Dcplb.h12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
Ddef_LPBlackfin.h635 #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high macro