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Searched refs:CPLB_USER_RD (Results 1 – 6 of 6) sorted by relevance

/arch/blackfin/include/asm/
Dcplb.h12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
14 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
15 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY…
47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
49 # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
102 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
Dpgtable.h54 #define _PAGE_RD (CPLB_USER_RD)
56 #define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
Ddef_LPBlackfin.h618 #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access macro
660 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
/arch/blackfin/kernel/cplb-mpu/
Dcplbinit.c49 icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB; in generate_cplb_tables_cpu()
60 icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); in generate_cplb_tables_cpu()
67 dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD; in generate_cplb_tables_cpu()
69 icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD; in generate_cplb_tables_cpu()
Dcplbmgr.c131 d_data |= CPLB_USER_RD; in dcplb_miss()
142 d_data |= CPLB_USER_RD | CPLB_USER_WR; in dcplb_miss()
153 d_data |= CPLB_USER_RD; in dcplb_miss()
232 i_data |= CPLB_USER_RD; in icplb_miss()
243 i_data |= CPLB_USER_RD; in icplb_miss()
263 i_data |= CPLB_USER_RD; in icplb_miss()
/arch/blackfin/kernel/
Dcplbinfo.c61 (data & CPLB_USER_RD) ? 'Y' : 'N', in cplbinfo_show()