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Searched refs:CPLB_USER_WR (Results 1 – 5 of 5) sorted by relevance

/arch/blackfin/include/asm/
Dpgtable.h55 #define _PAGE_WR (CPLB_USER_WR)
56 #define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
Ddef_LPBlackfin.h646 #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write macro
660 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
Dcplb.h23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY…
/arch/blackfin/kernel/cplb-mpu/
Dcplbmgr.c59 return !!(data & CPLB_USER_WR); in write_permitted()
142 d_data |= CPLB_USER_RD | CPLB_USER_WR; in dcplb_miss()
157 d_data |= CPLB_USER_WR; in dcplb_miss()
/arch/blackfin/kernel/
Dcplbinfo.c62 (data & CPLB_USER_WR) ? 'Y' : 'N', in cplbinfo_show()