Searched refs:CPLB_WT (Results 1 – 4 of 4) sorted by relevance
28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)95 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
658 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ macro
113 d_data |= CPLB_L1_AOW | CPLB_WT; in dcplb_miss()289 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && in dcplb_protection_fault()364 d_data |= CPLB_L1_AOW | CPLB_WT; in set_mask_dcplbs()
38 d_cache |= CPLB_L1_AOW | CPLB_WT; in generate_cplb_tables_cpu()