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Searched refs:D1Ar5 (Results 1 – 15 of 15) sorted by relevance

/arch/metag/tbx/
Dtbictxfpu.S142 GETD D1Ar5, [D1Ar3++]
143 MOV D0Ar6, D1Ar5
144 LSL D1Re0, D1Ar5, #8
146 AND D1Ar5, D1Ar5, #LO(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
147 OR D1Re0, D1Re0, D1Ar5
149 MOV D1Ar5, TXDEFR
150 ANDMT D1Ar5, D1Ar5, #HI(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
151 ANDMB D1Ar5, D1Ar5, #LO(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
152 OR D1Re0, D1Re0, D1Ar5
156 MOV D1Ar5, TXMODE
[all …]
Dtbitimer.S65 MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
69 ASR D1Ar5,D0Ar6,#31 /* Sign extend D0Ar6 into D1Ar5 */
70 SETLNZ [A0.3],D0Ar6,D1Ar5 /* ___TBITime(B/I)=-Start if enable */
90 MOV D1Ar5,#0 /* Timer GET request */
94 ADD D1Re0,D1Ar3,D1Ar5 /* to 64-bit signed extend time */
114 MOV D1Ar5,#TIMER_ADD_BIT /* Timer ADD request */
146 MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
185 LSRS D1Ar5,D1Ar5,#1 /* Carry = SET, Zero = !ADD */
193 LSRS D1Ar5,D1Ar5,#1 /* Carry = SET, Zero = !ADD */
200 ASR D1Ar5,D0Ar6,#31 /* Sign extend D0Ar6 into D1Ar5 */
Dtbipcx.S85 MOVT D1Ar5,#HI(___TBIBoingExit) /* Go here to return */
86 ADD D1Ar5,D1Ar5,#LO(___TBIBoingExit)
91 SETL [A0.2],D0Ar6,D1Ar5 /* Push header fields */
95 MOV D1Ar5,#0
96 SETL [A0.3++],D0Ar6,D1Ar5 /* Zero CT register states */
97 SETL [A0.3++],D0Ar6,D1Ar5
179 MOVT D1Ar5,#TBICTX_FPAC_BIT /* Copy FPActive into FPAC */
181 ORNZ D0Ar2,D0Ar2,D1Ar5
191 GETL D1Ar5,D0Ar6,[A1LbP] /* D0Ar6 = ___pTBIs[1] */
196 GETL D1Ar5,D0Ar6,[A1GbP] /* D0Ar6 = ___pTBIs[1] */
[all …]
Dtbisoft.S131 XOR D1Ar5,D1Ar5,D1Ar5 /* D1Ar5 = 0 */
133 SWAP D1Ar5,TXMASKI /* D1Ar5 <-> TXMASKI */
135 OR TXMASKI,D1Ar5,D1Ar3 /* New TXMASKI */
159 MOV PC,D1Ar5 /* Jump to fnMain */
206 MOV D1Ar5,A1GbP /* Same A1GbP */
Dtbictx.S108 GETL D0Ar6,D1Ar5,[D1Ar1+#TBICTX_Ext_AX2] /* Get A0.2, A1.2 state */
113 SETL [A0.2++],D0Ar6,D1Ar5 /* Save A0.2, A1.2 state */
133 MOV D1Ar5,TXL2START
138 SETL [A0.2++],D0Ar6,D1Ar5 /* Save 8*1 bytes */
140 MOV D1Ar5,TXL2END
194 MOV D1Ar5,TXDRSIZE
195 SETL [A0.2++],D0Ar6,D1Ar5 /* Save 8*1 bytes */
264 GETL D0Ar6,D1Ar5,[D0Re0++] /* Restore A0.2, A1.2 state */
270 SETD [D0Ar6+#TBICTX_Ext_AX2_U1],D1Ar5
272 SETL [D1Ar1+#TBICTX_Ext_AX2],D0Ar6,D1Ar5
[all …]
/arch/metag/lib/
Dmemcpy.S33 ANDS D1Ar5, D1Ar1, #7 ! test destination alignment
42 ADD D1Ar5, D1Ar5, #1 ! dest is aligned when D1Ar5 reaches #8
45 CMP D1Ar5, #8
53 LSR D1Ar5, D1Ar3, #3 ! D1Ar5 = number of 8 byte blocks
59 LSRS D1Ar5, D1Ar3, #5 ! D1Ar5 = number of 32 byte blocks
61 SUB TXRPT, D1Ar5, #1
65 GETL D0Ar6, D1Ar5, [A1.2++]
67 SETL [A0.2++], D0Ar6, D1Ar5
69 GETL D0Ar6, D1Ar5, [A1.2++]
71 SETL [A0.2++], D0Ar6, D1Ar5
[all …]
Dmemmove.S15 MOV D1Ar5, D0Ar2
16 CMP D1Ar1, D1Ar5
34 MOV D1Ar5, D1Ar1
37 ANDS D1Ar5, D1Ar5, #7
43 LSR D1Ar5, D1Ar3, #3
48 SUBS D1Ar5, D1Ar5, #1
70 SUBS D1Ar5, D1Ar5, #1
76 LSR D1Ar5, D1Ar3, #3
133 SUBS D1Ar5, D1Ar5, #1
170 SUBS D1Ar5, D1Ar5, #1
[all …]
Dmemset.S20 ! boundary, or the length of the string if less than 8, in D1Ar5
21 MOV D0Ar2,#8 ! Need 8 - N in D1Ar5 ...
22 SUB D1Ar5,D0Ar2,D0Ar4 ! ... subtract N
23 CMP D1Ar3,D1Ar5
24 MOVMI D1Ar5,D1Ar3
50 MOV D1Ar5,D1Ar3
63 ! D1Ar5 should be burst size (<= D1Ar3)
66 SUBS D1Ar3,D1Ar3,D1Ar5 ! Reduce count
67 ADD D1Ar1,D1Ar1,D1Ar5 ! Advance pointer to end of area
68 MULW D1Ar5,D1Ar5,#4 ! Scale to (1*4), (2*4), (3*4)
[all …]
Ddiv64.S26 ADD D1Ar5,D1Ar3,D1Ar3
27 ADDCS D1Ar5,D1Ar5,#1
28 CMP D1Ar5,D1Ar3
33 MOV D1Ar3,D1Ar5
43 MOV D1Ar5,D0Ar6
51 ADD D1Ar5,D1Ar5,D1Re0
52 ADDCS D1Ar5,D1Ar5,#1
70 MOV D1Re0,D1Ar5
Dmuldi3.S26 LSR D1Ar5,D0Ar6,#16
31 ADD D1Re0,D1Re0,D1Ar5
38 LSR D1Ar5,D0Ar6,#16
41 ADD D1Re0,D1Re0,D1Ar5
Dcopy_page.S14 GETL D0Ar6,D1Ar5,[D0Ar2++]
16 SETL [D1Ar1++],D0Ar6,D1Ar5
Ddivsi3.S73 FFB D1Ar5,D1Ar1 ! Find first bit of Au
74 ANDN D1Ar5,D1Ar5,#31 ! Handle exceptional case.
75 ORN D1Ar5,D1Ar5,#31 ! if N bit set, set to 31
79 SUBS D1Ar3,D1Ar5,D1Ar3 ! calculate diff, ffbA - ffbB
/arch/metag/kernel/
Dftrace_stub.S31 GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
55 GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
Dhead.S29 MOV D1Ar5,#0
/arch/metag/include/asm/
Dmetag_regs.h109 #define D1Ar5 D1.1 macro