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Searched refs:D1Re0 (Results 1 – 23 of 23) sorted by relevance

/arch/metag/lib/
Dmemmove.S23 MOV D1Re0, D0Ar2
25 ADD D0Ar2, D1Re0, D1Ar3
46 GETL D0Re0, D1Re0, [--A1.2]
47 SETL [--A0.2], D0Re0, D1Re0
54 GETB D1Re0, [--A1.2]
55 SETB [--A0.2], D1Re0
96 GETL D0Re0, D1Re0, [--A1.2]
112 ! form 64-bit data in D0Re0, D1Re0
113 MOV D1Re0, D0Re0
114 ! D1Re0 << gap-size
[all …]
Dmuldi3.S18 MULD D1Re0,D1Ar1,D0Ar4 ! (a 2^48 + b 2^32)(y 2^16 + z 2^0)
20 ADD D1Re0,D1Re0,D0Re0
29 ADDCS D1Re0,D1Re0,#1
31 ADD D1Re0,D1Re0,D1Ar5
34 ADD D1Re0,D1Re0,D0Ar6
41 ADD D1Re0,D1Re0,D1Ar5
42 ADDCS D1Re0,D1Re0,#1
Ddiv64.S16 MOV D1Re0,D1Ar1
22 MOV D1Re0,#0
35 ADD D1Re0,D1Re0,D1Re0
36 ADDCS D1Re0,D1Re0,#1
41 ORS A0.3,D1Re0,D0Re0
51 ADD D1Ar5,D1Ar5,D1Re0
58 LSL A0.3,D1Re0,#31
60 LSR D1Re0,D1Re0,#1
66 ORS A0.3,D1Re0,D0Re0
70 MOV D1Re0,D1Ar5
[all …]
Dmemcpy.S23 GETB D1Re0, [A1.2++]
24 SETB [A0.2++], D1Re0
64 GETL D0Re0, D1Re0, [A1.2++]
66 SETL [A0.2++], D0Re0, D1Re0
68 GETL D0Re0, D1Re0, [A1.2++]
70 SETL [A0.2++], D0Re0, D1Re0
95 GETL D0Re0, D1Re0, [A1.2]
115 MOV D0Re0, D1Re0
119 ! form 64-bit data in D0Re0, D1Re0
121 MOV D1Re0, D0Ar2
[all …]
Ddivsi3.S15 MOV D1Re0,D0Ar2 ! Au already in A1Ar1, Bu -> D1Re0
31 MOV D1Re0,D0Ar2 ! A already in A1Ar1, B -> D1Re0
33 XOR D0Ar4,D1Ar1,D1Re0 ! D0Ar4 -ive if result is -ive
35 ABS D1Re0,D1Re0 ! abs(B) -> Bu
37 CMP D1Ar1,D1Re0 ! Is ( Au > Bu )?
39 CMPHI D1Re0,D1Ar3 ! OR ( (Au & (~3)) <= (Bu << 2) )?
40 LSLSHI D1Ar3,D1Re0,#1 ! Buq = Bu << 1
49 CMP D1Ar1,D1Re0 ! ( A >= Bu )?
51 SUBCC D1Ar1,D1Ar1,D1Re0 ! and A -= Bu
61 !! D1Re0 is the input Bu value, this gets trashed
[all …]
Dashrdi3.S12 MOV D1Re0,D1Ar1
23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 ASR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 ASR D1Re0,D1Re0,#31 ! HI = HI >> 31
Dashldi3.S12 MOV D1Re0,D1Ar1
21 LSL D1Re0,D1Re0,D1Ar3 ! HI = HI << COUNT
23 OR D1Re0,D1Re0,D0Ar6 ! HI = HI | TMP
30 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
Dlshrdi3.S12 MOV D1Re0,D1Ar1
23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 MOV D1Re0,#0 ! HI = 0
Dmodsi3.S32 MOV D1Re0,A0.2 ! Recover A
34 ORS D1Re0,D1Re0,D1Re0 ! Was A negative?
Dclear_page.S12 MOV D1Re0,#0
14 SETL [D1Ar1++],D0Re0,D1Re0
Dcopy_page.S13 GETL D0Re0,D1Re0,[D0Ar2++]
15 SETL [D1Ar1++],D0Re0,D1Re0
/arch/metag/tbx/
Dtbiroot.S49 GETL D0Re0,D1Re0,[A1LbP] /* Base of root block table */
50 SWAPNZ D0Re0,D1Re0 /* Swap if asked */
68 MOV D1Re0,TXSTATUS /* Are we privileged or int? */
71 ANDT D1Re0,D1Re0,#HI(TXSTATUS_ISTAT_BIT) /* +TXSTATUS_PSTAT_BIT) */
72 LSL D1Re0,D1Re0,#TBID_ISTAT_S-TXSTATUS_ISTAT_S
78 XOR D1Re0,D1Re0,D1Re0
Dtbidefr.S69 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
75 LSLGT D1Re0, D1RtP, D1Ar3
86 XOR D1Re0, D1Re0, #-1 /* Prepare mask for acknowledge (avoids stall) */
91 AND D1.5, D1.5, D1Re0
139 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
144 ORGT D1Re0, D1Re0, #1
145 LSLGT D1Re0, D1Re0, D1Ar3
156 OR D0Re0, D0Re0, D1Re0
157 XOR TXDEFR, D0Re0, D1Re0
Dtbipcx.S80 MOV D1Re0,D1Ar1 /* and set result to arg */
111 MOV PC,D1Re0 /* Jump to handler */
117 MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
119 GETL D0Re0,D1Re0,[D1Re0+#TBICTX_DX-TBICTX_BYTES]
126 SETL [A0StP+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
127 ADD D1Re0,A0StP,#TBICTX_AX /* Address AX save area */
130 MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
222 GETD D1Re0,[D0Ar6+D0Re0] /* Get address for Handler */
248 GETL D0Re0,D1Re0,[A0FrP+#TBICTX_Flags]/* Get Flags:SaveMask, CurrPC */
251 MOV PCX,D1Re0 /* Set resumption PC */
[all …]
Dtbisoft.S82 MOVT D1Re0,#HI($LSwitchExit) /* ASync resume point here */
83 ADD D1Re0,D1Re0,#LO($LSwitchExit)
86 SETL [A0StP++],D0Re0,D1Re0 /* Push header fields */
89 MOV D1Re0,#0 /* resume of the thread */
91 SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrRPT, CurrBPOBITS, */
92 SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrMODE, CurrDIVTIME */
101 MOV D1Re0,D1Ar1
130 MOV D1Re0,D1Ar1
198 MOV D1Re0,#0 /* pCtx:0 is default Arg1:Arg2 */
224 MOV D1Ar1,D1Re0 /* Pass TBIRES args to call */
[all …]
Dtbictxfpu.S144 LSL D1Re0, D1Ar5, #8
145 ANDT D1Re0, D1Re0, #HI(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
147 OR D1Re0, D1Re0, D1Ar5
152 OR D1Re0, D1Re0, D1Ar5
153 MOV TXDEFR, D1Re0
Dtbitimer.S94 ADD D1Re0,D1Ar3,D1Ar5 /* to 64-bit signed extend time */
95 ADDCS D1Re0,D1Re0,#1 /* Support borrow too */
119 ASR D1Re0,D0Ar2,#31 /* Sign extend negated delta */
121 ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
151 ASR D1Re0,D0Ar2,#31 /* Sign extend delta */
153 ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
Dtbicore.S41 GETL D0Re0,D1Re0,[A1LbP]
114 MOV D1Re0,#0 /* Prepare to disable ints */
116 SWAP D1Re0,TXMASKI /* Really stop ints */
128 MOV TXMASKI,D1Re0 /* Allow ints */
Dtbictx.S49 MOV D1Re0,D1Ar1 /* with less Ints in TrigMask */
70 MOV D1Re0,D1.5
256 MOV D1Re0,D0Ar2 /* Keep flags in D1Re0 */
261 TSTT D1Re0,#TBICTX_XEXT_BIT /* Check for XEXT bit */
275 TSTT D1Re0,#TBICTX_XDX8_BIT /* Get extended DX regs? */
283 TSTT D1Re0,#TBICTX_XAXX_BIT /* Get extended AX regs? */
290 TSTT D1Re0,#TBICTX_XHL2_BIT /* Get hardware-loop regs? */
303 TSTT D1Re0,#TBICTX_XTDP_BIT /* Get per-thread DSP regs? */
/arch/metag/kernel/
Dftrace_stub.S44 MOVT D1Re0,#HI(_ftrace_stub)
45 ADD D1Re0,D1Re0,#LO(_ftrace_stub)
46 CMP D1Ar3,D1Re0
Dtbiunexp.S12 XOR TXMASKI,D1Re0,D1Re0 ! Turn off BGNDHALT handling!
19 GETL D0Re0,D1Re0,[--A0StP] ! Get result
Dhead.S26 MOV D1Re0,#0
56 MOV D1Re0,#0
57 SETD [D0Re0], D1Re0
/arch/metag/include/asm/
Dmetag_regs.h107 #define D1Re0 D1.0 macro