Searched refs:DIV4_DDR (Results 1 – 3 of 3) sorted by relevance
| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-shx3.c | 62 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
111 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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| D | clock-sh7785.c | 66 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
128 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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| D | clock-sh7786.c | 68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
136 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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