Home
last modified time | relevance | path

Searched refs:DMA14_IRQ_STATUS (Results 1 – 6 of 6) sorted by relevance

/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h531 #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ macro
DcdefBF538.h872 #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
873 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h738 #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register … macro
DcdefBF54x_base.h1239 #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1240 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h1824 #define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */ macro
DcdefBF60x_base.h865 #define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
866 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)