Searched refs:DMA15_IRQ_STATUS (Results 1 – 6 of 6) sorted by relevance
545 #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ macro
898 #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)899 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
754 #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register … macro
1268 #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)1269 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1845 #define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */ macro
902 #define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)903 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)