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Searched refs:DMA1_2_IRQ_STATUS (Results 1 – 2 of 2) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h352 #define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */ macro
DcdefBF561.h601 #define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
602 #define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)