Home
last modified time | relevance | path

Searched refs:DMA7_IRQ_STATUS (Results 1 – 14 of 14) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h295 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ macro
DcdefBF532.h352 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
353 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h328 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ macro
DcdefBF512.h588 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
589 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h328 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ macro
DcdefBF522.h605 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
606 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h304 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register … macro
DcdefBF534.h567 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
568 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h305 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ macro
DcdefBF538.h686 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
687 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h328 #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */ macro
DcdefBF54x_base.h530 #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
531 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h1677 #define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */ macro
DcdefBF60x_base.h606 #define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
607 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)