Home
last modified time | relevance | path

Searched refs:DMEM_CONTROL (Results 1 – 9 of 9) sorted by relevance

/arch/blackfin/include/asm/
Dcplb.h126 #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
127 #define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
146 #define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
147 #define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
Dcdef_LPBlackfin.h19 #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
20 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
Ddpmc.h419 PM_CORE_PUSH(0, DMEM_CONTROL);
616 PM_CORE_POP(0, DMEM_CONTROL)
Ddef_LPBlackfin.h238 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ macro
/arch/blackfin/mach-bf561/
Dsecondary.S73 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
75 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
/arch/blackfin/mach-common/
Dcache-c.c80 bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, in bfin_dcache_init()
Dhead.S82 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
84 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
Dentry.S376 P4.L = LO(DMEM_CONTROL);
377 P4.H = HI(DMEM_CONTROL);
1203 P4.L = LO(DMEM_CONTROL);
1204 P4.H = HI(DMEM_CONTROL);
/arch/blackfin/kernel/
Ddebug-mmrs.c671 D32(DMEM_CONTROL); in bfin_debug_mmrs_init()