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Searched refs:DM_INC (Results 1 – 5 of 5) sorted by relevance

/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7757.c133 .chcr = DM_INC | RS_ERS | 0x40000000 |
147 .chcr = DM_INC | RS_ERS | 0x40000000 |
164 .chcr = DM_INC | RS_ERS | 0x40000000 |
178 .chcr = DM_INC | RS_ERS | 0x40000000 |
192 .chcr = DM_INC | RS_ERS | 0x40000000 |
206 .chcr = DM_INC | RS_ERS | 0x40000000 |
223 .chcr = DM_INC | RS_ERS | 0x40000000 |
237 .chcr = DM_INC | RS_ERS | 0x40000000 |
251 .chcr = DM_INC | RS_ERS | 0x40000000 |
265 .chcr = DM_INC | RS_ERS | 0x40000000 |
[all …]
Dsetup-sh7724.c44 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
54 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
64 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
74 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
84 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
94 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
104 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
114 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
124 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
134 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
[all …]
Dsetup-sh7722.c38 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
48 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
58 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
68 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
78 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
88 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
/arch/sh/include/asm/
Ddma-register.h37 #define DM_INC 0x00004000 /* Destination addresses are incremented */ macro
/arch/sh/drivers/dma/
Ddma-sh.c28 #define RS_DUAL (DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))