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Searched refs:EBIU_DDRBWC2 (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h184 #define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */ macro
DcdefBF54x_base.h269 #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
270 #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c917 D32(EBIU_DDRBWC2); in bfin_debug_mmrs_init()