Searched refs:EBIU_SDBCTL (Results 1 – 14 of 14) sorted by relevance
177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
480 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)481 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
212 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
362 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)363 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
211 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
379 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)380 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
288 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
487 #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)488 #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
188 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
342 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)343 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
183 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ macro
476 #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)477 #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
823 #if defined(EBIU_SDBCTL) in get_mem_size()
894 D32(EBIU_SDBCTL); in bfin_debug_mmrs_init()896 D16(EBIU_SDBCTL); in bfin_debug_mmrs_init()