1 #include <linux/kernel.h>
2 #include <linux/init.h>
3 #include <linux/clocksource.h>
4 #include <linux/clockchips.h>
5 #include <linux/sched_clock.h>
6 #include <linux/interrupt.h>
7 #include <linux/irq.h>
8 #include <linux/io.h>
9 #include <asm/mach/time.h>
10 #include "soc.h"
11
12 /*************************************************************************
13 * Timer handling for EP93xx
14 *************************************************************************
15 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
16 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
17 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
18 * is free-running, and can't generate interrupts.
19 *
20 * The 508 kHz timers are ideal for use for the timer interrupt, as the
21 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
22 * timer (timer 3) to get as long sleep intervals as possible when using
23 * CONFIG_NO_HZ.
24 *
25 * The higher clock rate of timer 4 makes it a better choice than the
26 * other timers for use as clock source and for sched_clock(), providing
27 * a stable 40 bit time base.
28 *************************************************************************
29 */
30 #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
31 #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
32 #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
33 #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
34 #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
35 #define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
36 #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
37 #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
38 #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
39 #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
40 #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
41 #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
42 #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
43 #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
44 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
45 #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
46 #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
47 #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
48 #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
49
50 #define EP93XX_TIMER123_RATE 508469
51 #define EP93XX_TIMER4_RATE 983040
52
ep93xx_read_sched_clock(void)53 static u64 notrace ep93xx_read_sched_clock(void)
54 {
55 u64 ret;
56
57 ret = readl(EP93XX_TIMER4_VALUE_LOW);
58 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
59 return ret;
60 }
61
ep93xx_clocksource_read(struct clocksource * c)62 cycle_t ep93xx_clocksource_read(struct clocksource *c)
63 {
64 u64 ret;
65
66 ret = readl(EP93XX_TIMER4_VALUE_LOW);
67 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
68 return (cycle_t) ret;
69 }
70
ep93xx_clkevt_set_next_event(unsigned long next,struct clock_event_device * evt)71 static int ep93xx_clkevt_set_next_event(unsigned long next,
72 struct clock_event_device *evt)
73 {
74 /* Default mode: periodic, off, 508 kHz */
75 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
76 EP93XX_TIMER123_CONTROL_CLKSEL;
77
78 /* Clear timer */
79 writel(tmode, EP93XX_TIMER3_CONTROL);
80
81 /* Set next event */
82 writel(next, EP93XX_TIMER3_LOAD);
83 writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
84 EP93XX_TIMER3_CONTROL);
85 return 0;
86 }
87
88
ep93xx_clkevt_shutdown(struct clock_event_device * evt)89 static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
90 {
91 /* Disable timer */
92 writel(0, EP93XX_TIMER3_CONTROL);
93
94 return 0;
95 }
96
97 static struct clock_event_device ep93xx_clockevent = {
98 .name = "timer1",
99 .features = CLOCK_EVT_FEAT_ONESHOT,
100 .set_state_shutdown = ep93xx_clkevt_shutdown,
101 .set_state_oneshot = ep93xx_clkevt_shutdown,
102 .tick_resume = ep93xx_clkevt_shutdown,
103 .set_next_event = ep93xx_clkevt_set_next_event,
104 .rating = 300,
105 };
106
ep93xx_timer_interrupt(int irq,void * dev_id)107 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
108 {
109 struct clock_event_device *evt = dev_id;
110
111 /* Writing any value clears the timer interrupt */
112 writel(1, EP93XX_TIMER3_CLEAR);
113
114 evt->event_handler(evt);
115
116 return IRQ_HANDLED;
117 }
118
119 static struct irqaction ep93xx_timer_irq = {
120 .name = "ep93xx timer",
121 .flags = IRQF_TIMER | IRQF_IRQPOLL,
122 .handler = ep93xx_timer_interrupt,
123 .dev_id = &ep93xx_clockevent,
124 };
125
ep93xx_timer_init(void)126 void __init ep93xx_timer_init(void)
127 {
128 /* Enable and register clocksource and sched_clock on timer 4 */
129 writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
130 EP93XX_TIMER4_VALUE_HIGH);
131 clocksource_mmio_init(NULL, "timer4",
132 EP93XX_TIMER4_RATE, 200, 40,
133 ep93xx_clocksource_read);
134 sched_clock_register(ep93xx_read_sched_clock, 40,
135 EP93XX_TIMER4_RATE);
136
137 /* Set up clockevent on timer 3 */
138 setup_irq(IRQ_EP93XX_TIMER3, &ep93xx_timer_irq);
139 clockevents_config_and_register(&ep93xx_clockevent,
140 EP93XX_TIMER123_RATE,
141 1,
142 0xffffffffU);
143 }
144