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Searched refs:EXYNOS5_ARM_L2_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
Dpmu.c352 { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
474 { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
Dregs-pmu.h371 #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 macro