Home
last modified time | relevance | path

Searched refs:FIELD (Results 1 – 20 of 20) sorted by relevance

/arch/unicore32/include/mach/
Dregs-dmac.h56 #define DMAC_CHANNEL(ch) FIELD(1, 1, (ch))
58 #define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \
59 FIELD(0, 3, 9) | FIELD(0, 3, 6))
60 #define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \
61 FIELD(1, 3, 9) | FIELD(1, 3, 6))
62 #define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \
63 FIELD(2, 3, 9) | FIELD(2, 3, 6))
64 #define DMAC_CONTROL_DI FIELD(1, 1, 13)
65 #define DMAC_CONTROL_SI FIELD(1, 1, 12)
66 #define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0))
[all …]
Dregs-pm.h77 #define PM_PMCR_SFB FIELD(1, 1, 0)
78 #define PM_PMCR_IFB FIELD(1, 1, 1)
79 #define PM_PMCR_CFBSYS FIELD(1, 1, 2)
80 #define PM_PMCR_CFBDDR FIELD(1, 1, 3)
81 #define PM_PMCR_CFBVGA FIELD(1, 1, 4)
82 #define PM_PMCR_CFBDIVBCLK FIELD(1, 1, 5)
87 #define PM_PWER_GPIOHIGH FIELD(1, 1, 8)
91 #define PM_PWER_RTC FIELD(1, 1, 31)
93 #define PM_PCGR_BCLK64DDR FIELD(1, 1, 0)
94 #define PM_PCGR_BCLK64VGA FIELD(1, 1, 1)
[all …]
Dregs-sdc.h72 #define SDC_CCR_CLKEN FIELD(1, 1, 2)
76 #define SDC_CCR_PDIV(v) FIELD((v), 8, 8)
81 #define SDC_SRR_ENABLE FIELD(0, 1, 0)
85 #define SDC_SRR_DISABLE FIELD(1, 1, 0)
94 #define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0)
98 #define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0)
102 #define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0)
106 #define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0)
110 #define SDC_COMMAND_DATAREADY FIELD(1, 1, 2)
111 #define SDC_COMMAND_CMDEN FIELD(1, 1, 3)
[all …]
Dregs-umal.h135 #define UMAL_CFG1_TXENABLE FIELD(1, 1, 0)
136 #define UMAL_CFG1_RXENABLE FIELD(1, 1, 2)
137 #define UMAL_CFG1_TXFLOWCTL FIELD(1, 1, 4)
138 #define UMAL_CFG1_RXFLOWCTL FIELD(1, 1, 5)
139 #define UMAL_CFG1_CONFLPBK FIELD(1, 1, 8)
140 #define UMAL_CFG1_RESET FIELD(1, 1, 31)
146 #define UMAL_CFG2_FULLDUPLEX FIELD(1, 1, 0)
147 #define UMAL_CFG2_CRCENABLE FIELD(1, 1, 1)
148 #define UMAL_CFG2_PADCRC FIELD(1, 1, 2)
149 #define UMAL_CFG2_LENGTHCHECK FIELD(1, 1, 4)
[all …]
Dregs-spi.h32 #define SPI_SSIENR_EN FIELD(1, 1, 0)
37 #define SPI_SR_BUSY FIELD(1, 1, 0)
41 #define SPI_SR_TFNF FIELD(1, 1, 1)
45 #define SPI_SR_TFE FIELD(1, 1, 2)
49 #define SPI_SR_RFNE FIELD(1, 1, 3)
53 #define SPI_SR_RFF FIELD(1, 1, 4)
58 #define SPI_ISR_TXEIS FIELD(1, 1, 0)
62 #define SPI_ISR_TXOIS FIELD(1, 1, 1)
66 #define SPI_ISR_RXUIS FIELD(1, 1, 2)
70 #define SPI_ISR_RXOIS FIELD(1, 1, 3)
[all …]
Dregs-i2c.h38 #define I2C_CON_MASTER FIELD(1, 1, 0)
39 #define I2C_CON_SPEED_STD FIELD(1, 2, 1)
40 #define I2C_CON_SPEED_FAST FIELD(2, 2, 1)
41 #define I2C_CON_RESTART FIELD(1, 1, 5)
42 #define I2C_CON_SLAVEDISABLE FIELD(1, 1, 6)
44 #define I2C_DATACMD_READ FIELD(1, 1, 8)
45 #define I2C_DATACMD_WRITE FIELD(0, 1, 8)
47 #define I2C_DATACMD_DAT(v) FIELD((v), 8, 0)
49 #define I2C_ENABLE_ENABLE FIELD(1, 1, 0)
50 #define I2C_ENABLE_DISABLE FIELD(0, 1, 0)
[all …]
Dregs-ost.h50 #define OST_OSSR_M0 FIELD(1, 1, 0)
54 #define OST_OSSR_M1 FIELD(1, 1, 1)
58 #define OST_OSSR_M2 FIELD(1, 1, 2)
62 #define OST_OSSR_M3 FIELD(1, 1, 3)
67 #define OST_OIER_E0 FIELD(1, 1, 0)
71 #define OST_OIER_E1 FIELD(1, 1, 1)
75 #define OST_OIER_E2 FIELD(1, 1, 2)
79 #define OST_OIER_E3 FIELD(1, 1, 3)
84 #define OST_OWER_WME FIELD(1, 1, 0)
89 #define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10)
Dregs-ac97.h16 #define AC97_CODEC_REG(v) FIELD((v), 7, 16)
17 #define AC97_CODEC_VAL(v) FIELD((v), 16, 0)
18 #define AC97_CODEC_WRITECOMPLETE FIELD(1, 1, 2)
23 #define AC97_CMD_VPSAMPLE (FIELD(3, 2, 16) | FIELD(3, 2, 0))
28 #define AC97_CMD_FCSAMPLE FIELD(7, 3, 0)
30 #define AC97_CMD_RESET FIELD(1, 1, 0)
31 #define AC97_CMD_ENABLE FIELD(1, 1, 0)
32 #define AC97_CMD_DISABLE FIELD(0, 1, 0)
Dregs-resetc.h16 #define RESETC_SWRR_SRB FIELD(1, 1, 0)
21 #define RESETC_RSSR_HWR FIELD(1, 1, 0)
25 #define RESETC_RSSR_SWR FIELD(1, 1, 1)
29 #define RESETC_RSSR_WDR FIELD(1, 1, 2)
33 #define RESETC_RSSR_SMR FIELD(1, 1, 3)
Dregs-nand.h73 #define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
74 #define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
75 #define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
76 #define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
77 #define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
78 #define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)
Dregs-pci.h85 #define PCIBRI_CTLx_AT FIELD(1, 1, 2)
86 #define PCIBRI_CTLx_PREF FIELD(1, 1, 1)
87 #define PCIBRI_CTLx_MRL FIELD(1, 1, 0)
89 #define PCIBRI_BARx_ADDR FIELD(0xFFFFFFFC, 30, 2)
90 #define PCIBRI_BARx_IO FIELD(1, 1, 0)
91 #define PCIBRI_BARx_MEM FIELD(0, 1, 0)
93 #define PCIBRI_CMD_IO FIELD(1, 1, 0)
94 #define PCIBRI_CMD_MEM FIELD(1, 1, 1)
Dregs-rtc.h24 #define RTC_RTSR_AL FIELD(1, 1, 0)
28 #define RTC_RTSR_HZ FIELD(1, 1, 1)
32 #define RTC_RTSR_ALE FIELD(1, 1, 2)
36 #define RTC_RTSR_HZE FIELD(1, 1, 3)
Dregs-unigfx.h180 #define UDE_CFG_DST8 FIELD(0x0, 2, 8)
181 #define UDE_CFG_DST16 FIELD(0x1, 2, 8)
182 #define UDE_CFG_DST24 FIELD(0x2, 2, 8)
183 #define UDE_CFG_DST32 FIELD(0x3, 2, 8)
188 #define UDE_CFG_GDEN_ENABLE FIELD(1, 1, 3)
192 #define UDE_CFG_VDEN_ENABLE FIELD(1, 1, 4)
196 #define UDE_CFG_CDEN_ENABLE FIELD(1, 1, 5)
200 #define UDE_CFG_TIMEUP_ENABLE FIELD(1, 1, 6)
Dbitfield.h21 #define FIELD(val, vmask, vshift) (((val) & ((UData(1) << (vmask)) - 1)) << (vshift)) macro
/arch/x86/crypto/sha-mb/
Dsha1_mb_mgr_datastruct.S61 #FIELD _plaintext, 8, 8 # pointer to plaintext
62 #FIELD _ciphertext, 8, 8 # pointer to ciphertext
63 #FIELD _IV, 16, 8 # IV
64 #FIELD _keys, 8, 8 # pointer to keys
65 #FIELD _len, 4, 4 # length in bytes
66 #FIELD _status, 4, 4 # status enumeration
67 #FIELD _user_data, 8, 8 # pointer to user data
/arch/sparc/net/
Dbpf_jit_comp.c209 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \ argument
210 do { unsigned int _off = offsetof(STRUCT, FIELD); \
211 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \
215 #define emit_load32(BASE, STRUCT, FIELD, DEST) \ argument
216 do { unsigned int _off = offsetof(STRUCT, FIELD); \
217 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \
221 #define emit_load16(BASE, STRUCT, FIELD, DEST) \ argument
222 do { unsigned int _off = offsetof(STRUCT, FIELD); \
223 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \
227 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \ argument
[all …]
/arch/x86/kvm/
Dvmx.c637 #define FIELD(number, name) [number] = VMCS12_OFFSET(name) macro
702 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
703 FIELD(POSTED_INTR_NV, posted_intr_nv),
704 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
705 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
706 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
707 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
708 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
709 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
710 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
[all …]
/arch/unicore32/include/asm/
Dgpio.h90 if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR))) in gpio_to_irq()
/arch/unicore32/kernel/
Dpci.c55 | FIELD(value, 8, (where&3)*8), PCICFG_DATA); in puv3_write_config()
59 | FIELD(value, 16, (where&2)*8), PCICFG_DATA); in puv3_write_config()
Dirq.c307 writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR); in init_IRQ()