| /arch/sparc/include/asm/ |
| D | visasm.h | 16 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
22 297: wr %g0, FPRS_FEF, %fprs; \
38 andcc %o5, FPRS_FEF, %g0; \
42 297: wr %o5, FPRS_FEF, %fprs;
59 " " : : "i" (FPRS_FEF|FPRS_DU) : in save_and_clear_fpu()
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| /arch/sparc/kernel/ |
| D | rtrap_64.S | 39 andcc %l5, FPRS_FEF, %g0
295 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
298 andcc %l2, FPRS_FEF, %g0
303 wr %g1, FPRS_FEF, %fprs
327 5: wr %g0, FPRS_FEF, %fprs
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| D | unaligned_64.c | 552 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_ldf_stq()
553 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_ldf_stq()
634 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in handle_lddfmna()
635 current_thread_info()->fpsaved[0] = FPRS_FEF; in handle_lddfmna()
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| D | fpu_traps.S | 11 andcc %g5, FPRS_FEF, %g0
24 wr %g0, FPRS_FEF, %fprs
25 andcc %g5, FPRS_FEF, %g0
191 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
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| D | signal32.c | 435 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
459 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_frame32()
566 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
590 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame32()
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| D | signal_64.c | 161 fenab = (current_thread_info()->fpsaved[0] & FPRS_FEF); in sparc64_get_context()
367 if (current_thread_info()->fpsaved[0] & FPRS_FEF) in setup_rt_frame()
384 if (current_thread_info()->fpsaved[0] & FPRS_FEF) { in setup_rt_frame()
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| D | ptrace_64.c | 368 if (fprs & FPRS_FEF) { in fpregs64_get()
432 fprs |= (FPRS_FEF | FPRS_DL | FPRS_DU); in fpregs64_set()
709 if (fprs & FPRS_FEF) { in fpregs32_get()
785 fprs |= (FPRS_FEF | FPRS_DL); in fpregs32_set()
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| D | process_64.c | 717 if (fprs & FPRS_FEF) { in dump_fpu()
737 if(fprs & FPRS_FEF) { in dump_fpu()
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| D | prom_irqtrans.c | 365 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| /arch/sparc/lib/ |
| D | xor.S | 27 andcc %o5, FPRS_FEF|FPRS_DU, %g0
32 0: wr %g0, FPRS_FEF, %fprs
96 andcc %o5, FPRS_FEF|FPRS_DU, %g0
101 0: wr %g0, FPRS_FEF, %fprs
162 andcc %o5, FPRS_FEF|FPRS_DU, %g0
167 0: wr %g0, FPRS_FEF, %fprs
248 andcc %o5, FPRS_FEF|FPRS_DU, %g0
253 0: wr %g0, FPRS_FEF, %fprs
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| D | VISsave.S | 46 mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5
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| D | U3memcpy.S | 13 #define FPRS_FEF 0x04 macro
15 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
17 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
19 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
20 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | NG4memcpy.S | 13 #define FPRS_FEF 0x04 macro
20 andcc %o5, FPRS_FEF, %g0; \
22 wr %g0, FPRS_FEF, %fprs; \
28 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
31 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | NG2memcpy.S | 15 #define FPRS_FEF 0x04 macro
17 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
19 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
21 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
22 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| D | U1memcpy.S | 15 #define FPRS_FEF 0x04 macro
17 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
19 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
21 #define VISEntry rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
22 #define VISExit and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| /arch/sparc/include/uapi/asm/ |
| D | pstate.h | 74 #define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */ macro
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| /arch/sparc/math-emu/ |
| D | math_64.c | 417 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in do_mathemu()
418 current_thread_info()->fpsaved[0] = FPRS_FEF; in do_mathemu()
|