1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9 struct vm86;
10
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
17 #include <asm/page.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
25
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
32
33 /*
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
36 *
37 * Based on this we disable the IP header alignment in network drivers.
38 */
39 #define NET_IP_ALIGN 0
40
41 #define HBP_NUM 4
42 /*
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
45 */
current_text_addr(void)46 static inline void *current_text_addr(void)
47 {
48 void *pc;
49
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
51
52 return pc;
53 }
54
55 /*
56 * These alignment constraints are for performance in the vSMP case,
57 * but in the task_struct case we must also meet hardware imposed
58 * alignment requirements of the FPU state:
59 */
60 #ifdef CONFIG_X86_VSMP
61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
63 #else
64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
65 # define ARCH_MIN_MMSTRUCT_ALIGN 0
66 #endif
67
68 enum tlb_infos {
69 ENTRIES,
70 NR_INFO
71 };
72
73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
80
81 /*
82 * CPU type and hardware bug flags. Kept separately for each CPU.
83 * Members of this structure are referenced in head.S, so think twice
84 * before touching them. [mj]
85 */
86
87 struct cpuinfo_x86 {
88 __u8 x86; /* CPU family */
89 __u8 x86_vendor; /* CPU vendor */
90 __u8 x86_model;
91 __u8 x86_stepping;
92 #ifdef CONFIG_X86_32
93 char wp_works_ok; /* It doesn't on 386's */
94
95 /* Problems on some 486Dx4's and old 386's: */
96 char rfu;
97 char pad0;
98 char pad1;
99 #else
100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 int x86_tlbsize;
102 #endif
103 __u8 x86_virt_bits;
104 __u8 x86_phys_bits;
105 /* CPUID returned core id bits: */
106 __u8 x86_coreid_bits;
107
108 __u8 x86_cache_bits;
109 /* Max extended CPUID function supported: */
110 __u32 extended_cpuid_level;
111 /* Maximum supported CPUID level, -1=no CPUID: */
112 int cpuid_level;
113 __u32 x86_capability[NCAPINTS + NBUGINTS];
114 char x86_vendor_id[16];
115 char x86_model_id[64];
116 /* in KB - valid for CPUS which support this call: */
117 unsigned int x86_cache_size;
118 int x86_cache_alignment; /* In bytes */
119 /* Cache QoS architectural values: */
120 int x86_cache_max_rmid; /* max index */
121 int x86_cache_occ_scale; /* scale to bytes */
122 int x86_power;
123 unsigned long loops_per_jiffy;
124 /* cpuid returned max cores value: */
125 u16 x86_max_cores;
126 u16 apicid;
127 u16 initial_apicid;
128 u16 x86_clflush_size;
129 /* number of cores as seen by the OS: */
130 u16 booted_cores;
131 /* Physical processor id: */
132 u16 phys_proc_id;
133 /* Core id: */
134 u16 cpu_core_id;
135 /* Compute unit id */
136 u8 compute_unit_id;
137 /* Index into per_cpu list: */
138 u16 cpu_index;
139 u32 microcode;
140 };
141
142 #define X86_VENDOR_INTEL 0
143 #define X86_VENDOR_CYRIX 1
144 #define X86_VENDOR_AMD 2
145 #define X86_VENDOR_UMC 3
146 #define X86_VENDOR_CENTAUR 5
147 #define X86_VENDOR_TRANSMETA 7
148 #define X86_VENDOR_NSC 8
149 #define X86_VENDOR_NUM 9
150
151 #define X86_VENDOR_UNKNOWN 0xff
152
153 /*
154 * capabilities of CPUs
155 */
156 extern struct cpuinfo_x86 boot_cpu_data;
157 extern struct cpuinfo_x86 new_cpu_data;
158
159 extern struct tss_struct doublefault_tss;
160 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
161 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
162
163 #ifdef CONFIG_SMP
164 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
165 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
166 #else
167 #define cpu_info boot_cpu_data
168 #define cpu_data(cpu) boot_cpu_data
169 #endif
170
171 extern const struct seq_operations cpuinfo_op;
172
173 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
174
175 extern void cpu_detect(struct cpuinfo_x86 *c);
176
l1tf_pfn_limit(void)177 static inline unsigned long long l1tf_pfn_limit(void)
178 {
179 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
180 }
181
182 extern void early_cpu_init(void);
183 extern void identify_boot_cpu(void);
184 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
185 extern void print_cpu_info(struct cpuinfo_x86 *);
186 void print_cpu_msr(struct cpuinfo_x86 *);
187 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
188 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
189 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
190
191 extern void detect_extended_topology(struct cpuinfo_x86 *c);
192 extern void detect_ht(struct cpuinfo_x86 *c);
193
194 #ifdef CONFIG_X86_32
195 extern int have_cpuid_p(void);
196 #else
have_cpuid_p(void)197 static inline int have_cpuid_p(void)
198 {
199 return 1;
200 }
201 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)202 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
203 unsigned int *ecx, unsigned int *edx)
204 {
205 /* ecx is often an input as well as an output. */
206 asm volatile("cpuid"
207 : "=a" (*eax),
208 "=b" (*ebx),
209 "=c" (*ecx),
210 "=d" (*edx)
211 : "0" (*eax), "2" (*ecx)
212 : "memory");
213 }
214
215 #define native_cpuid_reg(reg) \
216 static inline unsigned int native_cpuid_##reg(unsigned int op) \
217 { \
218 unsigned int eax = op, ebx, ecx = 0, edx; \
219 \
220 native_cpuid(&eax, &ebx, &ecx, &edx); \
221 \
222 return reg; \
223 }
224
225 /*
226 * Native CPUID functions returning a single datum.
227 */
228 native_cpuid_reg(eax)
native_cpuid_reg(ebx)229 native_cpuid_reg(ebx)
230 native_cpuid_reg(ecx)
231 native_cpuid_reg(edx)
232
233 static inline void load_cr3(pgd_t *pgdir)
234 {
235 write_cr3(__pa(pgdir));
236 }
237
238 #ifdef CONFIG_X86_32
239 /* This is the TSS defined by the hardware. */
240 struct x86_hw_tss {
241 unsigned short back_link, __blh;
242 unsigned long sp0;
243 unsigned short ss0, __ss0h;
244 unsigned long sp1;
245
246 /*
247 * We don't use ring 1, so ss1 is a convenient scratch space in
248 * the same cacheline as sp0. We use ss1 to cache the value in
249 * MSR_IA32_SYSENTER_CS. When we context switch
250 * MSR_IA32_SYSENTER_CS, we first check if the new value being
251 * written matches ss1, and, if it's not, then we wrmsr the new
252 * value and update ss1.
253 *
254 * The only reason we context switch MSR_IA32_SYSENTER_CS is
255 * that we set it to zero in vm86 tasks to avoid corrupting the
256 * stack if we were to go through the sysenter path from vm86
257 * mode.
258 */
259 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
260
261 unsigned short __ss1h;
262 unsigned long sp2;
263 unsigned short ss2, __ss2h;
264 unsigned long __cr3;
265 unsigned long ip;
266 unsigned long flags;
267 unsigned long ax;
268 unsigned long cx;
269 unsigned long dx;
270 unsigned long bx;
271 unsigned long sp;
272 unsigned long bp;
273 unsigned long si;
274 unsigned long di;
275 unsigned short es, __esh;
276 unsigned short cs, __csh;
277 unsigned short ss, __ssh;
278 unsigned short ds, __dsh;
279 unsigned short fs, __fsh;
280 unsigned short gs, __gsh;
281 unsigned short ldt, __ldth;
282 unsigned short trace;
283 unsigned short io_bitmap_base;
284
285 } __attribute__((packed));
286 #else
287 struct x86_hw_tss {
288 u32 reserved1;
289 u64 sp0;
290 u64 sp1;
291 u64 sp2;
292 u64 reserved2;
293 u64 ist[7];
294 u32 reserved3;
295 u32 reserved4;
296 u16 reserved5;
297 u16 io_bitmap_base;
298
299 } __attribute__((packed)) ____cacheline_aligned;
300 #endif
301
302 /*
303 * IO-bitmap sizes:
304 */
305 #define IO_BITMAP_BITS 65536
306 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
307 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
308 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
309 #define INVALID_IO_BITMAP_OFFSET 0x8000
310
311 struct tss_struct {
312 /*
313 * The hardware state:
314 */
315 struct x86_hw_tss x86_tss;
316
317 /*
318 * The extra 1 is there because the CPU will access an
319 * additional byte beyond the end of the IO permission
320 * bitmap. The extra byte must be all 1 bits, and must
321 * be within the limit.
322 */
323 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
324
325 /*
326 * Space for the temporary SYSENTER stack:
327 */
328 unsigned long SYSENTER_stack[64];
329
330 } ____cacheline_aligned;
331
332 DECLARE_PER_CPU_SHARED_ALIGNED_USER_MAPPED(struct tss_struct, cpu_tss);
333
334 #ifdef CONFIG_X86_32
335 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
336 #endif
337
338 /*
339 * Save the original ist values for checking stack pointers during debugging
340 */
341 struct orig_ist {
342 unsigned long ist[7];
343 };
344
345 #ifdef CONFIG_X86_64
346 DECLARE_PER_CPU(struct orig_ist, orig_ist);
347
348 union irq_stack_union {
349 char irq_stack[IRQ_STACK_SIZE];
350 /*
351 * GCC hardcodes the stack canary as %gs:40. Since the
352 * irq_stack is the object at %gs:0, we reserve the bottom
353 * 48 bytes of the irq stack for the canary.
354 */
355 struct {
356 char gs_base[40];
357 unsigned long stack_canary;
358 };
359 };
360
361 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
362 DECLARE_INIT_PER_CPU(irq_stack_union);
363
364 DECLARE_PER_CPU(char *, irq_stack_ptr);
365 DECLARE_PER_CPU(unsigned int, irq_count);
366 extern asmlinkage void ignore_sysret(void);
367 #else /* X86_64 */
368 #ifdef CONFIG_CC_STACKPROTECTOR
369 /*
370 * Make sure stack canary segment base is cached-aligned:
371 * "For Intel Atom processors, avoid non zero segment base address
372 * that is not aligned to cache line boundary at all cost."
373 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
374 */
375 struct stack_canary {
376 char __pad[20]; /* canary at %gs:20 */
377 unsigned long canary;
378 };
379 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
380 #endif
381 /*
382 * per-CPU IRQ handling stacks
383 */
384 struct irq_stack {
385 u32 stack[THREAD_SIZE/sizeof(u32)];
386 } __aligned(THREAD_SIZE);
387
388 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
389 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
390 #endif /* X86_64 */
391
392 extern unsigned int xstate_size;
393
394 struct perf_event;
395
396 struct thread_struct {
397 /* Cached TLS descriptors: */
398 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
399 unsigned long sp0;
400 unsigned long sp;
401 #ifdef CONFIG_X86_32
402 unsigned long sysenter_cs;
403 #else
404 unsigned short es;
405 unsigned short ds;
406 unsigned short fsindex;
407 unsigned short gsindex;
408 #endif
409 #ifdef CONFIG_X86_32
410 unsigned long ip;
411 #endif
412 #ifdef CONFIG_X86_64
413 unsigned long fsbase;
414 unsigned long gsbase;
415 #else
416 /*
417 * XXX: this could presumably be unsigned short. Alternatively,
418 * 32-bit kernels could be taught to use fsindex instead.
419 */
420 unsigned long fs;
421 unsigned long gs;
422 #endif
423
424 /* Save middle states of ptrace breakpoints */
425 struct perf_event *ptrace_bps[HBP_NUM];
426 /* Debug status used for traps, single steps, etc... */
427 unsigned long debugreg6;
428 /* Keep track of the exact dr7 value set by the user */
429 unsigned long ptrace_dr7;
430 /* Fault info: */
431 unsigned long cr2;
432 unsigned long trap_nr;
433 unsigned long error_code;
434 #ifdef CONFIG_VM86
435 /* Virtual 86 mode info */
436 struct vm86 *vm86;
437 #endif
438 /* IO permissions: */
439 unsigned long *io_bitmap_ptr;
440 unsigned long iopl;
441 /* Max allowed port in the bitmap, in bytes: */
442 unsigned io_bitmap_max;
443
444 /* Floating point and extended processor state */
445 struct fpu fpu;
446 /*
447 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
448 * the end.
449 */
450 };
451
452 /*
453 * Set IOPL bits in EFLAGS from given mask
454 */
native_set_iopl_mask(unsigned mask)455 static inline void native_set_iopl_mask(unsigned mask)
456 {
457 #ifdef CONFIG_X86_32
458 unsigned int reg;
459
460 asm volatile ("pushfl;"
461 "popl %0;"
462 "andl %1, %0;"
463 "orl %2, %0;"
464 "pushl %0;"
465 "popfl"
466 : "=&r" (reg)
467 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
468 #endif
469 }
470
471 static inline void
native_load_sp0(struct tss_struct * tss,struct thread_struct * thread)472 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
473 {
474 tss->x86_tss.sp0 = thread->sp0;
475 #ifdef CONFIG_X86_32
476 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
477 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
478 tss->x86_tss.ss1 = thread->sysenter_cs;
479 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
480 }
481 #endif
482 }
483
native_swapgs(void)484 static inline void native_swapgs(void)
485 {
486 #ifdef CONFIG_X86_64
487 asm volatile("swapgs" ::: "memory");
488 #endif
489 }
490
current_top_of_stack(void)491 static inline unsigned long current_top_of_stack(void)
492 {
493 #ifdef CONFIG_X86_64
494 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
495 #else
496 /* sp0 on x86_32 is special in and around vm86 mode. */
497 return this_cpu_read_stable(cpu_current_top_of_stack);
498 #endif
499 }
500
501 #ifdef CONFIG_PARAVIRT
502 #include <asm/paravirt.h>
503 #else
504 #define __cpuid native_cpuid
505 #define paravirt_enabled() 0
506 #define paravirt_has(x) 0
507
load_sp0(struct tss_struct * tss,struct thread_struct * thread)508 static inline void load_sp0(struct tss_struct *tss,
509 struct thread_struct *thread)
510 {
511 native_load_sp0(tss, thread);
512 }
513
514 #define set_iopl_mask native_set_iopl_mask
515 #endif /* CONFIG_PARAVIRT */
516
517 typedef struct {
518 unsigned long seg;
519 } mm_segment_t;
520
521
522 /* Free all resources held by a thread. */
523 extern void release_thread(struct task_struct *);
524
525 unsigned long get_wchan(struct task_struct *p);
526
527 /*
528 * Generic CPUID function
529 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
530 * resulting in stale register contents being returned.
531 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)532 static inline void cpuid(unsigned int op,
533 unsigned int *eax, unsigned int *ebx,
534 unsigned int *ecx, unsigned int *edx)
535 {
536 *eax = op;
537 *ecx = 0;
538 __cpuid(eax, ebx, ecx, edx);
539 }
540
541 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)542 static inline void cpuid_count(unsigned int op, int count,
543 unsigned int *eax, unsigned int *ebx,
544 unsigned int *ecx, unsigned int *edx)
545 {
546 *eax = op;
547 *ecx = count;
548 __cpuid(eax, ebx, ecx, edx);
549 }
550
551 /*
552 * CPUID functions returning a single datum
553 */
cpuid_eax(unsigned int op)554 static inline unsigned int cpuid_eax(unsigned int op)
555 {
556 unsigned int eax, ebx, ecx, edx;
557
558 cpuid(op, &eax, &ebx, &ecx, &edx);
559
560 return eax;
561 }
562
cpuid_ebx(unsigned int op)563 static inline unsigned int cpuid_ebx(unsigned int op)
564 {
565 unsigned int eax, ebx, ecx, edx;
566
567 cpuid(op, &eax, &ebx, &ecx, &edx);
568
569 return ebx;
570 }
571
cpuid_ecx(unsigned int op)572 static inline unsigned int cpuid_ecx(unsigned int op)
573 {
574 unsigned int eax, ebx, ecx, edx;
575
576 cpuid(op, &eax, &ebx, &ecx, &edx);
577
578 return ecx;
579 }
580
cpuid_edx(unsigned int op)581 static inline unsigned int cpuid_edx(unsigned int op)
582 {
583 unsigned int eax, ebx, ecx, edx;
584
585 cpuid(op, &eax, &ebx, &ecx, &edx);
586
587 return edx;
588 }
589
590 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
rep_nop(void)591 static __always_inline void rep_nop(void)
592 {
593 asm volatile("rep; nop" ::: "memory");
594 }
595
cpu_relax(void)596 static __always_inline void cpu_relax(void)
597 {
598 rep_nop();
599 }
600
601 #define cpu_relax_lowlatency() cpu_relax()
602
603 /* Stop speculative execution and prefetching of modified code. */
sync_core(void)604 static inline void sync_core(void)
605 {
606 int tmp;
607
608 #ifdef CONFIG_X86_32
609 /*
610 * Do a CPUID if available, otherwise do a jump. The jump
611 * can conveniently enough be the jump around CPUID.
612 */
613 asm volatile("cmpl %2,%1\n\t"
614 "jl 1f\n\t"
615 "cpuid\n"
616 "1:"
617 : "=a" (tmp)
618 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
619 : "ebx", "ecx", "edx", "memory");
620 #else
621 /*
622 * CPUID is a barrier to speculative execution.
623 * Prefetched instructions are automatically
624 * invalidated when modified.
625 */
626 asm volatile("cpuid"
627 : "=a" (tmp)
628 : "0" (1)
629 : "ebx", "ecx", "edx", "memory");
630 #endif
631 }
632
633 extern void select_idle_routine(const struct cpuinfo_x86 *c);
634 extern void init_amd_e400_c1e_mask(void);
635
636 extern unsigned long boot_option_idle_override;
637 extern bool amd_e400_c1e_detected;
638
639 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
640 IDLE_POLL};
641
642 extern void enable_sep_cpu(void);
643 extern int sysenter_setup(void);
644
645 extern void early_trap_init(void);
646 void early_trap_pf_init(void);
647
648 /* Defined in head.S */
649 extern struct desc_ptr early_gdt_descr;
650
651 extern void cpu_set_gdt(int);
652 extern void switch_to_new_gdt(int);
653 extern void load_percpu_segment(int);
654 extern void cpu_init(void);
655
get_debugctlmsr(void)656 static inline unsigned long get_debugctlmsr(void)
657 {
658 unsigned long debugctlmsr = 0;
659
660 #ifndef CONFIG_X86_DEBUGCTLMSR
661 if (boot_cpu_data.x86 < 6)
662 return 0;
663 #endif
664 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
665
666 return debugctlmsr;
667 }
668
update_debugctlmsr(unsigned long debugctlmsr)669 static inline void update_debugctlmsr(unsigned long debugctlmsr)
670 {
671 #ifndef CONFIG_X86_DEBUGCTLMSR
672 if (boot_cpu_data.x86 < 6)
673 return;
674 #endif
675 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
676 }
677
678 extern void set_task_blockstep(struct task_struct *task, bool on);
679
680 /* Boot loader type from the setup header: */
681 extern int bootloader_type;
682 extern int bootloader_version;
683
684 extern char ignore_fpu_irq;
685
686 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
687 #define ARCH_HAS_PREFETCHW
688 #define ARCH_HAS_SPINLOCK_PREFETCH
689
690 #ifdef CONFIG_X86_32
691 # define BASE_PREFETCH ""
692 # define ARCH_HAS_PREFETCH
693 #else
694 # define BASE_PREFETCH "prefetcht0 %P1"
695 #endif
696
697 /*
698 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
699 *
700 * It's not worth to care about 3dnow prefetches for the K6
701 * because they are microcoded there and very slow.
702 */
prefetch(const void * x)703 static inline void prefetch(const void *x)
704 {
705 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
706 X86_FEATURE_XMM,
707 "m" (*(const char *)x));
708 }
709
710 /*
711 * 3dnow prefetch to get an exclusive cache line.
712 * Useful for spinlocks to avoid one state transition in the
713 * cache coherency protocol:
714 */
prefetchw(const void * x)715 static inline void prefetchw(const void *x)
716 {
717 alternative_input(BASE_PREFETCH, "prefetchw %P1",
718 X86_FEATURE_3DNOWPREFETCH,
719 "m" (*(const char *)x));
720 }
721
spin_lock_prefetch(const void * x)722 static inline void spin_lock_prefetch(const void *x)
723 {
724 prefetchw(x);
725 }
726
727 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
728 TOP_OF_KERNEL_STACK_PADDING)
729
730 #ifdef CONFIG_X86_32
731 /*
732 * User space process size: 3GB (default).
733 */
734 #define TASK_SIZE PAGE_OFFSET
735 #define TASK_SIZE_MAX TASK_SIZE
736 #define STACK_TOP TASK_SIZE
737 #define STACK_TOP_MAX STACK_TOP
738
739 #define INIT_THREAD { \
740 .sp0 = TOP_OF_INIT_STACK, \
741 .sysenter_cs = __KERNEL_CS, \
742 .io_bitmap_ptr = NULL, \
743 }
744
745 extern unsigned long thread_saved_pc(struct task_struct *tsk);
746
747 /*
748 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
749 * This is necessary to guarantee that the entire "struct pt_regs"
750 * is accessible even if the CPU haven't stored the SS/ESP registers
751 * on the stack (interrupt gate does not save these registers
752 * when switching to the same priv ring).
753 * Therefore beware: accessing the ss/esp fields of the
754 * "struct pt_regs" is possible, but they may contain the
755 * completely wrong values.
756 */
757 #define task_pt_regs(task) \
758 ({ \
759 unsigned long __ptr = (unsigned long)task_stack_page(task); \
760 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
761 ((struct pt_regs *)__ptr) - 1; \
762 })
763
764 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
765
766 #else
767 /*
768 * User space process size. 47bits minus one guard page. The guard
769 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
770 * the highest possible canonical userspace address, then that
771 * syscall will enter the kernel with a non-canonical return
772 * address, and SYSRET will explode dangerously. We avoid this
773 * particular problem by preventing anything from being mapped
774 * at the maximum canonical address.
775 */
776 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
777
778 /* This decides where the kernel will search for a free chunk of vm
779 * space during mmap's.
780 */
781 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
782 0xc0000000 : 0xFFFFe000)
783
784 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
785 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
786 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
787 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
788
789 #define STACK_TOP TASK_SIZE
790 #define STACK_TOP_MAX TASK_SIZE_MAX
791
792 #define INIT_THREAD { \
793 .sp0 = TOP_OF_INIT_STACK \
794 }
795
796 /*
797 * Return saved PC of a blocked thread.
798 * What is this good for? it will be always the scheduler or ret_from_fork.
799 */
800 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
801
802 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
803 extern unsigned long KSTK_ESP(struct task_struct *task);
804
805 #endif /* CONFIG_X86_64 */
806
807 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
808 unsigned long new_sp);
809
810 /*
811 * This decides where the kernel will search for a free chunk of vm
812 * space during mmap's.
813 */
814 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
815
816 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
817
818 /* Get/set a process' ability to use the timestamp counter instruction */
819 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
820 #define SET_TSC_CTL(val) set_tsc_mode((val))
821
822 extern int get_tsc_mode(unsigned long adr);
823 extern int set_tsc_mode(unsigned int val);
824
825 /* Register/unregister a process' MPX related resource */
826 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
827 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
828
829 #ifdef CONFIG_X86_INTEL_MPX
830 extern int mpx_enable_management(void);
831 extern int mpx_disable_management(void);
832 #else
mpx_enable_management(void)833 static inline int mpx_enable_management(void)
834 {
835 return -EINVAL;
836 }
mpx_disable_management(void)837 static inline int mpx_disable_management(void)
838 {
839 return -EINVAL;
840 }
841 #endif /* CONFIG_X86_INTEL_MPX */
842
843 extern u16 amd_get_nb_id(int cpu);
844 extern u32 amd_get_nodes_per_socket(void);
845
hypervisor_cpuid_base(const char * sig,uint32_t leaves)846 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
847 {
848 uint32_t base, eax, signature[3];
849
850 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
851 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
852
853 if (!memcmp(sig, signature, 12) &&
854 (leaves == 0 || ((eax - base) >= leaves)))
855 return base;
856 }
857
858 return 0;
859 }
860
861 extern unsigned long arch_align_stack(unsigned long sp);
862 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
863
864 void default_idle(void);
865 #ifdef CONFIG_XEN
866 bool xen_set_default_idle(void);
867 #else
868 #define xen_set_default_idle 0
869 #endif
870
871 void stop_this_cpu(void *dummy);
872 void df_debug(struct pt_regs *regs, long error_code);
873
874 enum mds_mitigations {
875 MDS_MITIGATION_OFF,
876 MDS_MITIGATION_FULL,
877 MDS_MITIGATION_VMWERV,
878 };
879
880 enum taa_mitigations {
881 TAA_MITIGATION_OFF,
882 TAA_MITIGATION_UCODE_NEEDED,
883 TAA_MITIGATION_VERW,
884 TAA_MITIGATION_TSX_DISABLED,
885 };
886
887 #endif /* _ASM_X86_PROCESSOR_H */
888