| /arch/metag/lib/ |
| D | ashrdi3.S | 23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 ASR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 ASR D1Re0,D1Re0,#31 ! HI = HI >> 31
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| D | ashldi3.S | 21 LSL D1Re0,D1Re0,D1Ar3 ! HI = HI << COUNT
23 OR D1Re0,D1Re0,D0Ar6 ! HI = HI | TMP
30 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
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| D | lshrdi3.S | 23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 MOV D1Re0,#0 ! HI = 0
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| D | div64.S | 81 TSTT D1Ar1,#HI(0x80000000)
88 TSTT D1Ar3,#HI(0x80000000)
96 TSTT D1.5,#HI(0x80000000)
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| /arch/blackfin/mach-bf609/ |
| D | dpm.S | 12 P0.H = HI(PM_STACK);
19 P0.H = HI(DPM0_RESTORE4);
25 P0.H = HI(DPM0_CTL);
27 R3.H = HI(0x00000010);
47 P0.h = HI(SEC_SCI_BASE + SEC_CSID);
52 P1.h = HI(SEC_END);
83 P0.H = HI(PM_STACK);
95 P0.H = HI(DPM0_CTL);
97 R3.H = HI(0x00000008);
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| /arch/hexagon/kernel/ |
| D | head.S | 43 r24.H = #HI(swapper_pg_dir)
53 r1.h = #HI(PAGE_OFFSET);
80 r1.h = #HI(_end);
81 r2.h = #HI(stext);
109 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
200 {r29.H = #HI(init_thread_union); r0.H = #HI(_THREAD_SIZE); }
209 { r0.H = #HI(__bss_start); r2.h = #HI(__bss_stop); }
217 r0.h = #HI(__phys_offset);
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| D | vm_entry.S | 74 R2.H = #HI(_THREAD_SIZE); } \
233 R1.H = #HI(CHandler); \
299 R26.H = #HI(do_work_pending);
378 R26.H = #HI(do_work_pending);
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| /arch/metag/tbx/ |
| D | tbictxfpu.S | 47 MOVT D0Ar4, #HI(METAC_CORE_ID)
55 ORT D0Ar4, D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT)
70 ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS)
71 ORT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODEWRITE_BIT)
78 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
145 ANDT D1Re0, D1Re0, #HI(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
150 ANDMT D1Ar5, D1Ar5, #HI(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
157 ANDMT D1Ar5, D1Ar5, #HI(~TXMODE_FPURMODE_BITS)
158 ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS|TXMODE_FPURMODEWRITE_BIT)
162 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
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| D | tbidefr.S | 50 ANDT D0.5, D0.5, #HI(0xFFFF0000)
52 ANDT D1Ar3, D1Ar3, #HI(0xFFFF0000)
57 ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
69 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
120 ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
139 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
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| D | tbipcx.S | 65 MOVT D0Re0,#HI(LINCORE_BASE)
72 MOVT D0FrT,#HI(___TBIBoingRTI+4)
85 MOVT D1Ar5,#HI(___TBIBoingExit) /* Go here to return */
108 MOVT A0.2, #HI($Lpcx_target)
149 TSTT D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
158 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
180 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
183 ANDT D1Ar3,D1Ar3,#HI(TXDIVTIME_IRQENC_BITS)
189 MOVT A1LbP,#HI(___pTBIs)
263 ANDST D1Ar3,D1Ar3,#HI(TXDIVTIME_RPMASK_BITS)/* !Z if RPDIRTY */
[all …]
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| D | tbitimer.S | 66 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
91 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
115 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
147 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
177 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Interrupt level timer? */
179 MOVT A1LbP,#HI(___TBITimes)
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| D | tbiroot.S | 46 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Bgnd or Int level? */
47 MOVT A1LbP,#HI(___pTBIs)
71 ANDT D1Re0,D1Re0,#HI(TXSTATUS_ISTAT_BIT) /* +TXSTATUS_PSTAT_BIT) */
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| D | tbisoft.S | 82 MOVT D1Re0,#HI($LSwitchExit) /* ASync resume point here */
155 MOVT A1LbP,#HI(__exit)
181 MOVT A1LbP,#HI(__exit)
193 MOVT D1RtP,#HI(___TBIStart) /* Start up code for new stack */
202 MOVT D1Ar1,#HI($LSwitchExit) /* Async restore code */
229 MOVT A1LbP,#HI(__exit)
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| D | tbicore.S | 39 MOVT A1LbP,#HI(___pTBISegs)
57 MOVT A1LbP,#HI(___pTBISegs)
115 MOVT A0.3,#HI(LINSYSEVENT_WR_ATOMIC_LOCK)
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| /arch/metag/kernel/ |
| D | head.S | 18 MOVT D0Re0,#HI(___pTBIs)
21 MOVT D0Re0,#HI(___pTBISegs)
34 MOVT A0StP,#HI(_init_thread_union)
37 MOVT D1RtP,#HI(_metag_start_kernel)
55 MOVT D0Re0,#HI(LINSYSEVENT_WR_ATOMIC_UNLOCK)
59 MOVT A0StP,#HI(_secondary_data_stack)
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| D | user_gateway.S | 39 MOVT D1Ar1,#HI(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
75 ANDT D0Re0,D0Re0,#HI(0x3f000000)
76 CMPT D0Re0,#HI(0x02000000)
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| D | ftrace_stub.S | 26 MOVT D1RtP,#HI(_ftrace_stub)
41 MOVT D0Re0,#HI(_ftrace_trace_function)
44 MOVT D1Re0,#HI(_ftrace_stub)
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| /arch/blackfin/include/asm/ |
| D | trace.h | 63 preg.H = HI(TBUFCTL); \
69 preg.H = HI(TBUFCTL); \
75 preg.H = HI(TBUFCTL); \
83 preg.H = HI(TBUFCTL); \
|
| D | entry.h | 43 preg.h = HI(CHIPID); \
116 P0.H = HI(ILAT); \
146 P0.H = HI(ILAT); \
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| D | blackfin.h | 56 #define HI(con32) (((con32) >> 16) & 0xFFFF) macro
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| /arch/mips/pci/ |
| D | ops-nile4.c | 12 #define HI(reg) (reg / 4 + 1) macro
45 vrc_pciregs[HI(NILE4_PCIERR)] = 0; in nile4_pcibios_config_access()
63 err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; in nile4_pcibios_config_access()
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| /arch/blackfin/mach-common/ |
| D | interrupt.S | 168 P0.H = HI(ILAT);
189 R1.H = HI(VEC_HWERR);
201 p0.h = HI(EBIU_ERRMST);
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| D | cache.S | 84 p0.H = HI(DSPID);
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| /arch/mn10300/kernel/ |
| D | kprobes.c | 93 #define HI (1 << 5) macro
106 /* 0 0 0 0 */ (NE | NC | CC | VC | GE | GT | HI),
108 /* 0 0 1 0 */ (NE | NS | CC | VC | LT | LE | HI),
114 /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI),
116 /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI),
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| /arch/arm/crypto/ |
| D | sha512-core.S_shipped | 61 # define HI 4
64 # define HI 0
155 ldr r8,[r0,#32+HI]
157 ldr r10, [r0,#48+HI]
159 ldr r12, [r0,#56+HI]
166 ldr r6,[r0,#0+HI]
168 ldr r4,[r0,#8+HI]
170 ldr r10, [r0,#16+HI]
172 ldr r12, [r0,#24+HI]
180 ldr r4,[r0,#40+HI]
[all …]
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