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1 #ifndef _ASM_X86_HYPERV_H
2 #define _ASM_X86_HYPERV_H
3 
4 #include <linux/types.h>
5 
6 /*
7  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
8  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
9  */
10 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS	0x40000000
11 #define HYPERV_CPUID_INTERFACE			0x40000001
12 #define HYPERV_CPUID_VERSION			0x40000002
13 #define HYPERV_CPUID_FEATURES			0x40000003
14 #define HYPERV_CPUID_ENLIGHTMENT_INFO		0x40000004
15 #define HYPERV_CPUID_IMPLEMENT_LIMITS		0x40000005
16 
17 #define HYPERV_HYPERVISOR_PRESENT_BIT		0x80000000
18 #define HYPERV_CPUID_MIN			0x40000005
19 #define HYPERV_CPUID_MAX			0x4000ffff
20 
21 /*
22  * Feature identification. EAX indicates which features are available
23  * to the partition based upon the current partition privileges.
24  */
25 
26 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
27 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE		(1 << 0)
28 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
29 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE	(1 << 1)
30 /* Partition reference TSC MSR is available */
31 #define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)
32 
33 /* A partition's reference time stamp counter (TSC) page */
34 #define HV_X64_MSR_REFERENCE_TSC		0x40000021
35 
36 /*
37  * There is a single feature flag that signifies the presence of the MSR
38  * that can be used to retrieve both the local APIC Timer frequency as
39  * well as the TSC frequency.
40  */
41 
42 /* Local APIC timer frequency MSR (HV_X64_MSR_APIC_FREQUENCY) is available */
43 #define HV_X64_MSR_APIC_FREQUENCY_AVAILABLE (1 << 11)
44 
45 /* TSC frequency MSR (HV_X64_MSR_TSC_FREQUENCY) is available */
46 #define HV_X64_MSR_TSC_FREQUENCY_AVAILABLE (1 << 11)
47 
48 /*
49  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
50  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
51  */
52 #define HV_X64_MSR_SYNIC_AVAILABLE		(1 << 2)
53 /*
54  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
55  * HV_X64_MSR_STIMER3_COUNT) available
56  */
57 #define HV_X64_MSR_SYNTIMER_AVAILABLE		(1 << 3)
58 /*
59  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
60  * are available
61  */
62 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE	(1 << 4)
63 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
64 #define HV_X64_MSR_HYPERCALL_AVAILABLE		(1 << 5)
65 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
66 #define HV_X64_MSR_VP_INDEX_AVAILABLE		(1 << 6)
67 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
68 #define HV_X64_MSR_RESET_AVAILABLE		(1 << 7)
69  /*
70   * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
71   * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
72   * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
73   */
74 #define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)
75 
76 /*
77  * Feature identification: EBX indicates which flags were specified at
78  * partition creation. The format is the same as the partition creation
79  * flag structure defined in section Partition Creation Flags.
80  */
81 #define HV_X64_CREATE_PARTITIONS		(1 << 0)
82 #define HV_X64_ACCESS_PARTITION_ID		(1 << 1)
83 #define HV_X64_ACCESS_MEMORY_POOL		(1 << 2)
84 #define HV_X64_ADJUST_MESSAGE_BUFFERS		(1 << 3)
85 #define HV_X64_POST_MESSAGES			(1 << 4)
86 #define HV_X64_SIGNAL_EVENTS			(1 << 5)
87 #define HV_X64_CREATE_PORT			(1 << 6)
88 #define HV_X64_CONNECT_PORT			(1 << 7)
89 #define HV_X64_ACCESS_STATS			(1 << 8)
90 #define HV_X64_DEBUGGING			(1 << 11)
91 #define HV_X64_CPU_POWER_MANAGEMENT		(1 << 12)
92 #define HV_X64_CONFIGURE_PROFILER		(1 << 13)
93 
94 /*
95  * Feature identification. EDX indicates which miscellaneous features
96  * are available to the partition.
97  */
98 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
99 #define HV_X64_MWAIT_AVAILABLE				(1 << 0)
100 /* Guest debugging support is available */
101 #define HV_X64_GUEST_DEBUGGING_AVAILABLE		(1 << 1)
102 /* Performance Monitor support is available*/
103 #define HV_X64_PERF_MONITOR_AVAILABLE			(1 << 2)
104 /* Support for physical CPU dynamic partitioning events is available*/
105 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE	(1 << 3)
106 /*
107  * Support for passing hypercall input parameter block via XMM
108  * registers is available
109  */
110 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE		(1 << 4)
111 /* Support for a virtual guest idle state is available */
112 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE		(1 << 5)
113 /* Guest crash data handler available */
114 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE		(1 << 10)
115 
116 /*
117  * Implementation recommendations. Indicates which behaviors the hypervisor
118  * recommends the OS implement for optimal performance.
119  */
120  /*
121   * Recommend using hypercall for address space switches rather
122   * than MOV to CR3 instruction
123   */
124 #define HV_X64_MWAIT_RECOMMENDED		(1 << 0)
125 /* Recommend using hypercall for local TLB flushes rather
126  * than INVLPG or MOV to CR3 instructions */
127 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED	(1 << 1)
128 /*
129  * Recommend using hypercall for remote TLB flushes rather
130  * than inter-processor interrupts
131  */
132 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED	(1 << 2)
133 /*
134  * Recommend using MSRs for accessing APIC registers
135  * EOI, ICR and TPR rather than their memory-mapped counterparts
136  */
137 #define HV_X64_APIC_ACCESS_RECOMMENDED		(1 << 3)
138 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
139 #define HV_X64_SYSTEM_RESET_RECOMMENDED		(1 << 4)
140 /*
141  * Recommend using relaxed timing for this partition. If used,
142  * the VM should disable any watchdog timeouts that rely on the
143  * timely delivery of external interrupts
144  */
145 #define HV_X64_RELAXED_TIMING_RECOMMENDED	(1 << 5)
146 
147 /* MSR used to identify the guest OS. */
148 #define HV_X64_MSR_GUEST_OS_ID			0x40000000
149 
150 /* MSR used to setup pages used to communicate with the hypervisor. */
151 #define HV_X64_MSR_HYPERCALL			0x40000001
152 
153 /* MSR used to provide vcpu index */
154 #define HV_X64_MSR_VP_INDEX			0x40000002
155 
156 /* MSR used to reset the guest OS. */
157 #define HV_X64_MSR_RESET			0x40000003
158 
159 /* MSR used to provide vcpu runtime in 100ns units */
160 #define HV_X64_MSR_VP_RUNTIME			0x40000010
161 
162 /* MSR used to read the per-partition time reference counter */
163 #define HV_X64_MSR_TIME_REF_COUNT		0x40000020
164 
165 /* MSR used to retrieve the TSC frequency */
166 #define HV_X64_MSR_TSC_FREQUENCY		0x40000022
167 
168 /* MSR used to retrieve the local APIC timer frequency */
169 #define HV_X64_MSR_APIC_FREQUENCY		0x40000023
170 
171 /* Define the virtual APIC registers */
172 #define HV_X64_MSR_EOI				0x40000070
173 #define HV_X64_MSR_ICR				0x40000071
174 #define HV_X64_MSR_TPR				0x40000072
175 #define HV_X64_MSR_APIC_ASSIST_PAGE		0x40000073
176 
177 /* Define synthetic interrupt controller model specific registers. */
178 #define HV_X64_MSR_SCONTROL			0x40000080
179 #define HV_X64_MSR_SVERSION			0x40000081
180 #define HV_X64_MSR_SIEFP			0x40000082
181 #define HV_X64_MSR_SIMP				0x40000083
182 #define HV_X64_MSR_EOM				0x40000084
183 #define HV_X64_MSR_SINT0			0x40000090
184 #define HV_X64_MSR_SINT1			0x40000091
185 #define HV_X64_MSR_SINT2			0x40000092
186 #define HV_X64_MSR_SINT3			0x40000093
187 #define HV_X64_MSR_SINT4			0x40000094
188 #define HV_X64_MSR_SINT5			0x40000095
189 #define HV_X64_MSR_SINT6			0x40000096
190 #define HV_X64_MSR_SINT7			0x40000097
191 #define HV_X64_MSR_SINT8			0x40000098
192 #define HV_X64_MSR_SINT9			0x40000099
193 #define HV_X64_MSR_SINT10			0x4000009A
194 #define HV_X64_MSR_SINT11			0x4000009B
195 #define HV_X64_MSR_SINT12			0x4000009C
196 #define HV_X64_MSR_SINT13			0x4000009D
197 #define HV_X64_MSR_SINT14			0x4000009E
198 #define HV_X64_MSR_SINT15			0x4000009F
199 
200 /*
201  * Synthetic Timer MSRs. Four timers per vcpu.
202  */
203 #define HV_X64_MSR_STIMER0_CONFIG		0x400000B0
204 #define HV_X64_MSR_STIMER0_COUNT		0x400000B1
205 #define HV_X64_MSR_STIMER1_CONFIG		0x400000B2
206 #define HV_X64_MSR_STIMER1_COUNT		0x400000B3
207 #define HV_X64_MSR_STIMER2_CONFIG		0x400000B4
208 #define HV_X64_MSR_STIMER2_COUNT		0x400000B5
209 #define HV_X64_MSR_STIMER3_CONFIG		0x400000B6
210 #define HV_X64_MSR_STIMER3_COUNT		0x400000B7
211 
212 /* Hyper-V guest crash notification MSR's */
213 #define HV_X64_MSR_CRASH_P0			0x40000100
214 #define HV_X64_MSR_CRASH_P1			0x40000101
215 #define HV_X64_MSR_CRASH_P2			0x40000102
216 #define HV_X64_MSR_CRASH_P3			0x40000103
217 #define HV_X64_MSR_CRASH_P4			0x40000104
218 #define HV_X64_MSR_CRASH_CTL			0x40000105
219 #define HV_X64_MSR_CRASH_CTL_NOTIFY		(1ULL << 63)
220 #define HV_X64_MSR_CRASH_PARAMS		\
221 		(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
222 
223 #define HV_X64_MSR_HYPERCALL_ENABLE		0x00000001
224 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT	12
225 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK	\
226 		(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
227 
228 /* Declare the various hypercall operations. */
229 #define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT		0x0008
230 
231 #define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE		0x00000001
232 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT	12
233 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK	\
234 		(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
235 
236 #define HV_X64_MSR_TSC_REFERENCE_ENABLE		0x00000001
237 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT	12
238 
239 #define HV_PROCESSOR_POWER_STATE_C0		0
240 #define HV_PROCESSOR_POWER_STATE_C1		1
241 #define HV_PROCESSOR_POWER_STATE_C2		2
242 #define HV_PROCESSOR_POWER_STATE_C3		3
243 
244 /* hypercall status code */
245 #define HV_STATUS_SUCCESS			0
246 #define HV_STATUS_INVALID_HYPERCALL_CODE	2
247 #define HV_STATUS_INVALID_HYPERCALL_INPUT	3
248 #define HV_STATUS_INVALID_ALIGNMENT		4
249 #define HV_STATUS_INSUFFICIENT_MEMORY		11
250 #define HV_STATUS_INVALID_CONNECTION_ID		18
251 #define HV_STATUS_INSUFFICIENT_BUFFERS		19
252 
253 typedef struct _HV_REFERENCE_TSC_PAGE {
254 	__u32 tsc_sequence;
255 	__u32 res1;
256 	__u64 tsc_scale;
257 	__s64 tsc_offset;
258 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
259 
260 /* Define the number of synthetic interrupt sources. */
261 #define HV_SYNIC_SINT_COUNT		(16)
262 /* Define the expected SynIC version. */
263 #define HV_SYNIC_VERSION_1		(0x1)
264 
265 #define HV_SYNIC_CONTROL_ENABLE		(1ULL << 0)
266 #define HV_SYNIC_SIMP_ENABLE		(1ULL << 0)
267 #define HV_SYNIC_SIEFP_ENABLE		(1ULL << 0)
268 #define HV_SYNIC_SINT_MASKED		(1ULL << 16)
269 #define HV_SYNIC_SINT_AUTO_EOI		(1ULL << 17)
270 #define HV_SYNIC_SINT_VECTOR_MASK	(0xFF)
271 
272 #endif
273