• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 #ifndef __MACH_SDK7786_FPGA_H
2 #define __MACH_SDK7786_FPGA_H
3 
4 #include <linux/io.h>
5 #include <linux/types.h>
6 #include <linux/bitops.h>
7 
8 #define SRSTR		0x000
9 #define  SRSTR_MAGIC	0x1971	/* Fixed magical read value */
10 
11 #define INTASR		0x010
12 #define INTAMR		0x020
13 #define MODSWR		0x030
14 #define INTTESTR	0x040
15 #define SYSSR		0x050
16 #define NRGPR		0x060
17 
18 #define NMISR		0x070
19 #define  NMISR_MAN_NMI	BIT(0)
20 #define  NMISR_AUX_NMI	BIT(1)
21 #define  NMISR_MASK	(NMISR_MAN_NMI | NMISR_AUX_NMI)
22 
23 #define NMIMR		0x080
24 #define  NMIMR_MAN_NMIM	BIT(0)	/* Manual NMI mask */
25 #define  NMIMR_AUX_NMIM	BIT(1)	/* Auxiliary NMI mask */
26 #define  NMIMR_MASK	(NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
27 
28 #define INTBSR		0x090
29 #define INTBMR		0x0a0
30 #define USRLEDR		0x0b0
31 #define MAPSWR		0x0c0
32 #define FPGAVR		0x0d0
33 #define FPGADR		0x0e0
34 #define PCBRR		0x0f0
35 #define RSR		0x100
36 #define EXTASR		0x110
37 #define SPCAR		0x120
38 #define INTMSR		0x130
39 
40 #define PCIECR		0x140
41 #define  PCIECR_PCIEMUX1	BIT(15)
42 #define  PCIECR_PCIEMUX0	BIT(14)
43 #define  PCIECR_PRST4		BIT(12) /* slot 4 card present */
44 #define  PCIECR_PRST3		BIT(11) /* slot 3 card present */
45 #define  PCIECR_PRST2		BIT(10) /* slot 2 card present */
46 #define  PCIECR_PRST1		BIT(9)  /* slot 1 card present */
47 #define  PCIECR_CLKEN		BIT(4)	/* oscillator enable */
48 
49 #define FAER		0x150
50 #define USRGPIR		0x160
51 
52 /* 0x170 reserved */
53 
54 #define LCLASR			0x180
55 #define  LCLASR_FRAMEN		BIT(15)
56 
57 #define  LCLASR_FPGA_SEL_SHIFT	12
58 #define  LCLASR_NAND_SEL_SHIFT	8
59 #define  LCLASR_NORB_SEL_SHIFT	4
60 #define  LCLASR_NORA_SEL_SHIFT	0
61 
62 #define  LCLASR_AREA_MASK	0x7
63 
64 #define  LCLASR_FPGA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
65 #define  LCLASR_NAND_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
66 #define  LCLASR_NORB_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
67 #define  LCLASR_NORA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
68 
69 #define SBCR		0x190
70 #define  SCBR_I2CMEN	BIT(0)	/* FPGA I2C master enable */
71 #define  SCBR_I2CCEN	BIT(1)	/* CPU I2C master enable */
72 
73 #define PWRCR		0x1a0
74 #define  PWRCR_SCISEL0	BIT(0)
75 #define  PWRCR_SCISEL1	BIT(1)
76 #define  PWRCR_SCIEN	BIT(2)	/* Serial port enable */
77 #define  PWRCR_PDWNACK	BIT(5)	/* Power down acknowledge */
78 #define  PWRCR_PDWNREQ	BIT(7)	/* Power down request */
79 #define  PWRCR_INT2	BIT(11)	/* INT2 connection to power manager */
80 #define  PWRCR_BUPINIT	BIT(13)	/* DDR backup initialize */
81 #define  PWRCR_BKPRST	BIT(15) /* Backup power reset */
82 
83 #define SPCBR		0x1b0
84 #define SPICR		0x1c0
85 #define SPIDR		0x1d0
86 #define I2CCR		0x1e0
87 #define I2CDR		0x1f0
88 #define FPGACR		0x200
89 #define IASELR1		0x210
90 #define IASELR2		0x220
91 #define IASELR3		0x230
92 #define IASELR4		0x240
93 #define IASELR5		0x250
94 #define IASELR6		0x260
95 #define IASELR7		0x270
96 #define IASELR8		0x280
97 #define IASELR9		0x290
98 #define IASELR10	0x2a0
99 #define IASELR11	0x2b0
100 #define IASELR12	0x2c0
101 #define IASELR13	0x2d0
102 #define IASELR14	0x2e0
103 #define IASELR15	0x2f0
104 /* 0x300 reserved */
105 #define IBSELR1		0x310
106 #define IBSELR2		0x320
107 #define IBSELR3		0x330
108 #define IBSELR4		0x340
109 #define IBSELR5		0x350
110 #define IBSELR6		0x360
111 #define IBSELR7		0x370
112 #define IBSELR8		0x380
113 #define IBSELR9		0x390
114 #define IBSELR10	0x3a0
115 #define IBSELR11	0x3b0
116 #define IBSELR12	0x3c0
117 #define IBSELR13	0x3d0
118 #define IBSELR14	0x3e0
119 #define IBSELR15	0x3f0
120 #define USRACR		0x400
121 #define BEEPR		0x410
122 #define USRLCDR		0x420
123 #define SMBCR		0x430
124 #define SMBDR		0x440
125 #define USBCR		0x450
126 #define AMSR		0x460
127 #define ACCR		0x470
128 #define SDIFCR		0x480
129 
130 /* arch/sh/boards/mach-sdk7786/fpga.c */
131 extern void __iomem *sdk7786_fpga_base;
132 extern void sdk7786_fpga_init(void);
133 
134 /* arch/sh/boards/mach-sdk7786/nmi.c */
135 extern void sdk7786_nmi_init(void);
136 
137 #define SDK7786_FPGA_REGADDR(reg)	(sdk7786_fpga_base + (reg))
138 
139 /*
140  * A convenience wrapper from register offset to internal I2C address,
141  * when the FPGA is in I2C slave mode.
142  */
143 #define SDK7786_FPGA_I2CADDR(reg)	((reg) >> 3)
144 
fpga_read_reg(unsigned int reg)145 static inline u16 fpga_read_reg(unsigned int reg)
146 {
147 	return ioread16(sdk7786_fpga_base + reg);
148 }
149 
fpga_write_reg(u16 val,unsigned int reg)150 static inline void fpga_write_reg(u16 val, unsigned int reg)
151 {
152 	iowrite16(val, sdk7786_fpga_base + reg);
153 }
154 
155 #endif /* __MACH_SDK7786_FPGA_H */
156