| /arch/mips/pci/ |
| D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
76 { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
[all …]
|
| D | fixup-ip32.c | 22 #define INTC MACEPCI_SHARED1_IRQ macro
29 {0, INTA0, INTB, INTC, INTD},
30 {0, INTA1, INTC, INTD, INTB},
31 {0, INTA2, INTD, INTB, INTC},
|
| D | fixup-capcella.c | 32 #define INTC PC104PLUS_INTC_IRQ macro
38 [14] = { -1, INTA, INTB, INTC, INTD }
|
| /arch/arm/mach-iop32x/ |
| D | em7210.c | 78 #define INTC IRQ_IOP32X_XINT2 macro
92 {INTC, INTC, INTC, INTC}, /* GD31244 */ in em7210_pci_map_irq()
94 {INTD, INTC, INTA, INTA}, /* NEC USB */ in em7210_pci_map_irq()
|
| D | glantank.c | 73 #define INTC IRQ_IOP32X_XINT2 macro
87 {INTC, INTC, INTC, INTC}, /* USB (NEC) */ in glantank_pci_map_irq()
|
| /arch/arm/mach-ixp4xx/ |
| D | nslu2-pci.c | 30 #define INTC 9 macro
37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in nslu2_pci_preinit()
46 IXP4XX_GPIO_IRQ(INTC), in nslu2_map_irq()
|
| D | miccpt-pci.c | 34 #define INTC 3 macro
42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in miccpt_pci_preinit()
52 IXP4XX_GPIO_IRQ(INTC), in miccpt_map_irq()
|
| D | avila-pci.c | 37 #define INTC 9 macro
44 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in avila_pci_preinit()
54 IXP4XX_GPIO_IRQ(INTC), in avila_map_irq()
|
| D | ixdp425-pci.c | 33 #define INTC 9 macro
41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in ixdp425_pci_preinit()
51 IXP4XX_GPIO_IRQ(INTC), in ixdp425_map_irq()
|
| D | fsg-pci.c | 31 #define INTC 5 macro
37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in fsg_pci_preinit()
44 IXP4XX_GPIO_IRQ(INTC), in fsg_map_irq()
|
| D | nas100d-pci.c | 30 #define INTC 9 macro
38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in nas100d_pci_preinit()
49 { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), in nas100d_map_irq()
|
| D | dsmg600-pci.c | 31 #define INTC 9 macro
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in dsmg600_pci_preinit()
52 { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), in dsmg600_map_irq()
|
| /arch/arc/boot/dts/ |
| D | axc001.dtsi | 73 * This INTC is actually connected to DW APB GPIO
74 * which acts as a wire between MB INTC and CPU INTC.
75 * GPIO INTC is configured in platform init code
76 * and here we mimic direct connection from MB INTC to
77 * CPU INTC, thus we set "interrupts = <7>" instead of
|
| D | axc003_idu.dtsi | 98 * This INTC is actually connected to DW APB GPIO
99 * which acts as a wire between MB INTC and CPU INTC.
100 * GPIO INTC is configured in platform init code
101 * and here we mimic direct connection from MB INTC to
102 * CPU INTC, thus we set "interrupts = <0 1>" instead of
|
| /arch/powerpc/boot/dts/ |
| D | holly.dts | 157 | The INTA, INTB, INTC, INTD are shared.
|
| D | katmai.dts | 309 * INTC: J2: 1-2
|