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1 /*
2  *  This file contains the hardware definitions of the Integrator.
3  *
4  *  Copyright (C) 1998-1999 ARM Limited.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19  */
20 #ifndef INTEGRATOR_HARDWARE_H
21 #define INTEGRATOR_HARDWARE_H
22 
23 /*
24  * Where in virtual memory the IO devices (timers, system controllers
25  * and so on)
26  */
27 #define IO_BASE			0xF0000000                 // VA of IO
28 #define IO_SIZE			0x0B000000                 // How much?
29 #define IO_START		INTEGRATOR_HDR_BASE        // PA of IO
30 
31 /* macro to get at IO space when running virtually */
32 #ifdef CONFIG_MMU
33 #define IO_ADDRESS(x)	(((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
34 #else
35 #define IO_ADDRESS(x)	(x)
36 #endif
37 
38 #define __io_address(n)		((void __iomem *)IO_ADDRESS(n))
39 
40 /*
41  *  Integrator memory map
42  */
43 #define INTEGRATOR_BOOT_ROM_LO          0x00000000
44 #define INTEGRATOR_BOOT_ROM_HI          0x20000000
45 #define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI	 /*  Normal position */
46 #define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
47 
48 /*
49  * New Core Modules have different amounts of SSRAM, the amount of SSRAM
50  * fitted can be found in HDR_STAT.
51  *
52  * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
53  * the minimum amount of SSRAM fitted on any core module.
54  *
55  * New Core Modules also alias the SSRAM.
56  *
57  */
58 #define INTEGRATOR_SSRAM_BASE           0x00000000
59 #define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
60 #define INTEGRATOR_SSRAM_SIZE           SZ_256K
61 
62 #define INTEGRATOR_FLASH_BASE           0x24000000
63 #define INTEGRATOR_FLASH_SIZE           SZ_32M
64 
65 #define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
66 #define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K
67 
68 /*
69  *  SDRAM is a SIMM therefore the size is not known.
70  */
71 #define INTEGRATOR_SDRAM_BASE           0x00040000
72 
73 #define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
74 #define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
75 #define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
76 #define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
77 #define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000
78 
79 /*
80  *  Logic expansion modules
81  *
82  */
83 #define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
84 #define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
85 #define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
86 #define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
87 #define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
88 
89 /*
90  * Integrator header card registers
91  */
92 #define INTEGRATOR_HDR_ID_OFFSET        0x00
93 #define INTEGRATOR_HDR_PROC_OFFSET      0x04
94 #define INTEGRATOR_HDR_OSC_OFFSET       0x08
95 #define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
96 #define INTEGRATOR_HDR_STAT_OFFSET      0x10
97 #define INTEGRATOR_HDR_LOCK_OFFSET      0x14
98 #define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
99 #define INTEGRATOR_HDR_INIT_OFFSET      0x24	 /*  CM9x6 */
100 #define INTEGRATOR_HDR_IC_OFFSET        0x40
101 #define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
102 #define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200
103 
104 #define INTEGRATOR_HDR_BASE             0x10000000
105 #define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
106 #define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
107 #define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
108 #define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
109 #define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
110 #define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
111 #define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
112 #define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
113 #define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
114 #define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
115 #define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
116 
117 #define INTEGRATOR_HDR_CTRL_LED         0x01
118 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
119 #define INTEGRATOR_HDR_CTRL_REMAP       0x04
120 #define INTEGRATOR_HDR_CTRL_RESET       0x08
121 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
122 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
123 #define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
124 #define INTEGRATOR_HDR_CTRL_SYNC        0x80
125 
126 #define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
127 #define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
128 #define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
129 #define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
130 #define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
131 #define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
132 #define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
133 #define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
134 #define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
135 #define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
136 #define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
137 #define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
138 #define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
139 #define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
140 #define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
141 #define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
142 #define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
143 #define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
144 #define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
145 #define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
146 #define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
147 #define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
148 #define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
149 #define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
150 #define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
151 #define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
152 #define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
153 #define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
154 #define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
155 #define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
156 #define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
157 #define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF
158 
159 #define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
160 #define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
161 #define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
162 #define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
163 #define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
164 #define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
165 #define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
166 #define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
167 #define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
168 #define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
169 #define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000
170 
171 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
172 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
173 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
174 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
175 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000
176 
177 #define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
178 
179 /*
180  * Integrator system registers
181  */
182 
183 /*
184  *  System Controller
185  */
186 #define INTEGRATOR_SC_ID_OFFSET         0x00
187 #define INTEGRATOR_SC_OSC_OFFSET        0x04
188 #define INTEGRATOR_SC_CTRLS_OFFSET      0x08
189 #define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
190 #define INTEGRATOR_SC_DEC_OFFSET        0x10
191 #define INTEGRATOR_SC_ARB_OFFSET        0x14
192 #define INTEGRATOR_SC_LOCK_OFFSET       0x1C
193 
194 #define INTEGRATOR_SC_BASE              0x11000000
195 #define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
196 #define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
197 #define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
198 #define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
199 #define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
200 #define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
201 #define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
202 #define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
203 
204 #define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
205 #define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
206 #define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
207 #define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
208 #define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
209 #define INTEGRATOR_SC_OSC_SYS_MASK      0xFF
210 
211 #define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
212 #define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
213 #define INTEGRATOR_SC_OSC_PCI_MASK      0x100
214 
215 #define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
216 #define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
217 #define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
218 #define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
219 #define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
220 #define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
221 #define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)
222 
223 /*
224  *  External Bus Interface
225  */
226 #define INTEGRATOR_EBI_BASE             0x12000000
227 
228 #define INTEGRATOR_EBI_CSR0_OFFSET      0x00
229 #define INTEGRATOR_EBI_CSR1_OFFSET      0x04
230 #define INTEGRATOR_EBI_CSR2_OFFSET      0x08
231 #define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
232 #define INTEGRATOR_EBI_LOCK_OFFSET      0x20
233 
234 #define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
235 #define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
236 #define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
237 #define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
238 #define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
239 
240 #define INTEGRATOR_EBI_8_BIT            0x00
241 #define INTEGRATOR_EBI_16_BIT           0x01
242 #define INTEGRATOR_EBI_32_BIT           0x02
243 #define INTEGRATOR_EBI_WRITE_ENABLE     0x04
244 #define INTEGRATOR_EBI_SYNC             0x08
245 #define INTEGRATOR_EBI_WS_2             0x00
246 #define INTEGRATOR_EBI_WS_3             0x10
247 #define INTEGRATOR_EBI_WS_4             0x20
248 #define INTEGRATOR_EBI_WS_5             0x30
249 #define INTEGRATOR_EBI_WS_6             0x40
250 #define INTEGRATOR_EBI_WS_7             0x50
251 #define INTEGRATOR_EBI_WS_8             0x60
252 #define INTEGRATOR_EBI_WS_9             0x70
253 #define INTEGRATOR_EBI_WS_10            0x80
254 #define INTEGRATOR_EBI_WS_11            0x90
255 #define INTEGRATOR_EBI_WS_12            0xA0
256 #define INTEGRATOR_EBI_WS_13            0xB0
257 #define INTEGRATOR_EBI_WS_14            0xC0
258 #define INTEGRATOR_EBI_WS_15            0xD0
259 #define INTEGRATOR_EBI_WS_16            0xE0
260 #define INTEGRATOR_EBI_WS_17            0xF0
261 
262 
263 #define INTEGRATOR_CT_BASE              0x13000000	 /*  Counter/Timers */
264 #define INTEGRATOR_IC_BASE              0x14000000	 /*  Interrupt Controller */
265 #define INTEGRATOR_RTC_BASE             0x15000000	 /*  Real Time Clock */
266 #define INTEGRATOR_UART0_BASE           0x16000000	 /*  UART 0 */
267 #define INTEGRATOR_UART1_BASE           0x17000000	 /*  UART 1 */
268 #define INTEGRATOR_KBD_BASE             0x18000000	 /*  Keyboard */
269 #define INTEGRATOR_MOUSE_BASE           0x19000000	 /*  Mouse */
270 
271 /*
272  *  LED's & Switches
273  */
274 #define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
275 #define INTEGRATOR_DBG_LEDS_OFFSET      0x04
276 #define INTEGRATOR_DBG_SWITCH_OFFSET    0x08
277 
278 #define INTEGRATOR_DBG_BASE             0x1A000000
279 #define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
280 #define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
281 #define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
282 
283 #define INTEGRATOR_AP_GPIO_BASE		0x1B000000	/* GPIO */
284 
285 #define INTEGRATOR_CP_MMC_BASE		0x1C000000	/* MMC */
286 #define INTEGRATOR_CP_AACI_BASE		0x1D000000	/* AACI */
287 #define INTEGRATOR_CP_ETH_BASE		0xC8000000	/* Ethernet */
288 #define INTEGRATOR_CP_GPIO_BASE		0xC9000000	/* GPIO */
289 #define INTEGRATOR_CP_SIC_BASE		0xCA000000	/* SIC */
290 #define INTEGRATOR_CP_CTL_BASE		0xCB000000	/* CP system control */
291 
292 /* PS2 Keyboard interface */
293 #define KMI0_BASE                       INTEGRATOR_KBD_BASE
294 
295 /* PS2 Mouse interface */
296 #define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
297 
298 /*
299  * Integrator Interrupt Controllers
300  *
301  *
302  * Offsets from interrupt controller base
303  *
304  * System Controller interrupt controller base is
305  *
306  * 	INTEGRATOR_IC_BASE + (header_number << 6)
307  *
308  * Core Module interrupt controller base is
309  *
310  * 	INTEGRATOR_HDR_IC
311  */
312 #define IRQ_STATUS                      0
313 #define IRQ_RAW_STATUS                  0x04
314 #define IRQ_ENABLE                      0x08
315 #define IRQ_ENABLE_SET                  0x08
316 #define IRQ_ENABLE_CLEAR                0x0C
317 
318 #define INT_SOFT_SET                    0x10
319 #define INT_SOFT_CLEAR                  0x14
320 
321 #define FIQ_STATUS                      0x20
322 #define FIQ_RAW_STATUS                  0x24
323 #define FIQ_ENABLE                      0x28
324 #define FIQ_ENABLE_SET                  0x28
325 #define FIQ_ENABLE_CLEAR                0x2C
326 
327 
328 /*
329  * LED's
330  */
331 #define GREEN_LED                       0x01
332 #define YELLOW_LED                      0x02
333 #define RED_LED                         0x04
334 #define GREEN_LED_2                     0x08
335 #define ALL_LEDS                        0x0F
336 
337 #define LED_BANK                        INTEGRATOR_DBG_LEDS
338 
339 /*
340  *  Timer definitions
341  *
342  *  Only use timer 1 & 2
343  *  (both run at 24MHz and will need the clock divider set to 16).
344  *
345  *  Timer 0 runs at bus frequency
346  */
347 #define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
348 #define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
349 #define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
350 
351 #define INTEGRATOR_CSR_BASE             0x10000000
352 #define INTEGRATOR_CSR_SIZE             0x10000000
353 
354 #endif /* INTEGRATOR_HARDWARE_H */
355