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Searched refs:IO_ADDRESS (Results 1 – 25 of 33) sorted by relevance

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/arch/arm/mach-gemini/
Dmm.c22 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
27 .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
32 .virtual = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
37 .virtual = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
42 .virtual = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
47 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
52 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
57 .virtual = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
62 .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
67 .virtual = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
[all …]
Dirq.c40 __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_ack_irq()
47 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
49 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
56 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
58 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
99 __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
100 __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
103 __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
104 __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
Dtime.c28 #define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
29 #define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
30 #define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
31 #define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
32 #define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
33 #define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
34 #define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
185 reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); in gemini_timer_init()
Ddevices.c23 .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
70 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS); in platform_register_pflash()
81 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); in platform_register_pflash()
84 __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); in platform_register_pflash()
Dreset.c22 IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); in gemini_restart()
/arch/arm/mach-realview/include/mach/
Dhardware.h36 #define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) macro
38 #define IO_ADDRESS(x) (x) macro
40 #define __io_address(n) IOMEM(IO_ADDRESS(n))
/arch/arm/mach-tegra/
Dreset.h43 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
47 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
51 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
Dreset.c41 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); in tegra_cpu_reset_handler_set()
42 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); in tegra_cpu_reset_handler_set()
65 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); in tegra_cpu_reset_handler_enable()
Dpm.c293 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), in tegra_suspend_enter_lp1()
295 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), in tegra_suspend_enter_lp1()
304 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, in tegra_suspend_exit_lp1()
/arch/arm/mach-realview/
Drealview_pb1176.c55 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
60 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
65 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
70 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
75 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
80 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
85 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
90 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
95 .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
102 .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
Drealview_pbx.c52 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
57 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
62 .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
67 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
72 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
77 .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
92 .virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
102 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
107 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
112 .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
Drealview_pb11mp.c53 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
58 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
63 .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
68 .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
73 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
78 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
83 .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
88 .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
95 .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
Drealview_pba8.c50 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
55 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_CPU_BASE),
60 .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_DIST_BASE),
65 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
70 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER0_1_BASE),
75 .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER2_3_BASE),
90 .virtual = IO_ADDRESS(REALVIEW_PBA8_UART0_BASE),
Drealview_eb.c53 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
58 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
63 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
68 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
73 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
78 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
85 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
95 .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
100 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
/arch/arm/mach-integrator/
Dintegrator_cp.c68 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
73 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
78 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
83 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
88 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
93 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
98 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
Dintegrator_ap.c84 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
89 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
94 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
99 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
Dhardware.h33 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) macro
35 #define IO_ADDRESS(x) (x) macro
38 #define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
/arch/arm/mach-versatile/include/mach/
Dhardware.h34 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) macro
36 #define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
/arch/arm/mach-lpc32xx/include/mach/
Dhardware.h28 #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ macro
31 #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
Dentry-macro.S25 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
/arch/arm/mach-lpc32xx/
Dcommon.c167 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
173 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
179 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
185 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
/arch/arm/mach-davinci/include/mach/
Dhardware.h31 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) macro
/arch/arm/mach-gemini/include/mach/
Dhardware.h69 #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) macro
Dentry-macro.S19 ldr \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
/arch/arm/mach-versatile/
Dcore.c133 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
138 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
143 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
148 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
155 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
163 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
171 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),

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