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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Definitions for the address map in the JUNKIO Asic
7  *
8  * Created with Information from:
9  *
10  * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
11  *
12  * and the Mach Sources
13  *
14  * Copyright (C) 199x  the Anonymous
15  * Copyright (C) 2002, 2003  Maciej W. Rozycki
16  */
17 
18 #ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
19 #define __ASM_MIPS_DEC_IOASIC_ADDRS_H
20 
21 #define IOASIC_SLOT_SIZE 0x00040000
22 
23 /*
24  * Address ranges decoded by the I/O ASIC for onboard devices.
25  */
26 #define IOASIC_SYS_ROM	(0*IOASIC_SLOT_SIZE)	/* system board ROM */
27 #define IOASIC_IOCTL	(1*IOASIC_SLOT_SIZE)	/* I/O ASIC */
28 #define IOASIC_ESAR	(2*IOASIC_SLOT_SIZE)	/* LANCE MAC address chip */
29 #define IOASIC_LANCE	(3*IOASIC_SLOT_SIZE)	/* LANCE Ethernet */
30 #define IOASIC_SCC0	(4*IOASIC_SLOT_SIZE)	/* SCC #0 */
31 #define IOASIC_VDAC_HI	(5*IOASIC_SLOT_SIZE)	/* VDAC (maxine) */
32 #define IOASIC_SCC1	(6*IOASIC_SLOT_SIZE)	/* SCC #1 (3min, 3max+) */
33 #define IOASIC_VDAC_LO	(7*IOASIC_SLOT_SIZE)	/* VDAC (maxine) */
34 #define IOASIC_TOY	(8*IOASIC_SLOT_SIZE)	/* RTC */
35 #define IOASIC_ISDN	(9*IOASIC_SLOT_SIZE)	/* ISDN (maxine) */
36 #define IOASIC_ERRADDR	(9*IOASIC_SLOT_SIZE)	/* bus error address (3max+) */
37 #define IOASIC_CHKSYN	(10*IOASIC_SLOT_SIZE)	/* ECC syndrome (3max+) */
38 #define IOASIC_ACC_BUS	(10*IOASIC_SLOT_SIZE)	/* ACCESS.bus (maxine) */
39 #define IOASIC_MCR	(11*IOASIC_SLOT_SIZE)	/* memory control (3max+) */
40 #define IOASIC_FLOPPY	(11*IOASIC_SLOT_SIZE)	/* FDC (maxine) */
41 #define IOASIC_SCSI	(12*IOASIC_SLOT_SIZE)	/* ASC SCSI */
42 #define IOASIC_FDC_DMA	(13*IOASIC_SLOT_SIZE)	/* FDC DMA (maxine) */
43 #define IOASIC_SCSI_DMA	(14*IOASIC_SLOT_SIZE)	/* ??? */
44 #define IOASIC_RES_15	(15*IOASIC_SLOT_SIZE)	/* unused? */
45 
46 
47 /*
48  * Offsets for I/O ASIC registers
49  * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
50  */
51 					/* all systems */
52 #define IO_REG_SCSI_DMA_P	0x00	/* SCSI DMA Pointer */
53 #define IO_REG_SCSI_DMA_BP	0x10	/* SCSI DMA Buffer Pointer */
54 #define IO_REG_LANCE_DMA_P	0x20	/* LANCE DMA Pointer */
55 #define IO_REG_SCC0A_T_DMA_P	0x30	/* SCC0A Transmit DMA Pointer */
56 #define IO_REG_SCC0A_R_DMA_P	0x40	/* SCC0A Receive DMA Pointer */
57 
58 					/* except Maxine */
59 #define IO_REG_SCC1A_T_DMA_P	0x50	/* SCC1A Transmit DMA Pointer */
60 #define IO_REG_SCC1A_R_DMA_P	0x60	/* SCC1A Receive DMA Pointer */
61 
62 					/* Maxine */
63 #define IO_REG_AB_T_DMA_P	0x50	/* ACCESS.bus Transmit DMA Pointer */
64 #define IO_REG_AB_R_DMA_P	0x60	/* ACCESS.bus Receive DMA Pointer */
65 #define IO_REG_FLOPPY_DMA_P	0x70	/* Floppy DMA Pointer */
66 #define IO_REG_ISDN_T_DMA_P	0x80	/* ISDN Transmit DMA Pointer */
67 #define IO_REG_ISDN_T_DMA_BP	0x90	/* ISDN Transmit DMA Buffer Pointer */
68 #define IO_REG_ISDN_R_DMA_P	0xa0	/* ISDN Receive DMA Pointer */
69 #define IO_REG_ISDN_R_DMA_BP	0xb0	/* ISDN Receive DMA Buffer Pointer */
70 
71 					/* all systems */
72 #define IO_REG_DATA_0		0xc0	/* System Data Buffer 0 */
73 #define IO_REG_DATA_1		0xd0	/* System Data Buffer 1 */
74 #define IO_REG_DATA_2		0xe0	/* System Data Buffer 2 */
75 #define IO_REG_DATA_3		0xf0	/* System Data Buffer 3 */
76 
77 					/* all systems */
78 #define IO_REG_SSR		0x100	/* System Support Register */
79 #define IO_REG_SIR		0x110	/* System Interrupt Register */
80 #define IO_REG_SIMR		0x120	/* System Interrupt Mask Reg. */
81 #define IO_REG_SAR		0x130	/* System Address Register */
82 
83 					/* Maxine */
84 #define IO_REG_ISDN_T_DATA	0x140	/* ISDN Xmit Data Register */
85 #define IO_REG_ISDN_R_DATA	0x150	/* ISDN Receive Data Register */
86 
87 					/* all systems */
88 #define IO_REG_LANCE_SLOT	0x160	/* LANCE I/O Slot Register */
89 #define IO_REG_SCSI_SLOT	0x170	/* SCSI Slot Register */
90 #define IO_REG_SCC0A_SLOT	0x180	/* SCC0A DMA Slot Register */
91 
92 					/* except Maxine */
93 #define IO_REG_SCC1A_SLOT	0x190	/* SCC1A DMA Slot Register */
94 
95 					/* Maxine */
96 #define IO_REG_AB_SLOT		0x190	/* ACCESS.bus DMA Slot Register */
97 #define IO_REG_FLOPPY_SLOT	0x1a0	/* Floppy Slot Register */
98 
99 					/* all systems */
100 #define IO_REG_SCSI_SCR		0x1b0	/* SCSI Partial-Word DMA Control */
101 #define IO_REG_SCSI_SDR0	0x1c0	/* SCSI DMA Partial Word 0 */
102 #define IO_REG_SCSI_SDR1	0x1d0	/* SCSI DMA Partial Word 1 */
103 #define IO_REG_FCTR		0x1e0	/* Free-Running Counter */
104 #define IO_REG_RES_31		0x1f0	/* unused */
105 
106 
107 /*
108  * The upper 16 bits of the System Support Register are a part of the
109  * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
110  * machines.  The exception is the Maxine, which makes use of the
111  * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
112  * wiring.
113  */
114 						/* all systems */
115 #define IO_SSR_SCC0A_TX_DMA_EN	(1<<31)		/* SCC0A transmit DMA enable */
116 #define IO_SSR_SCC0A_RX_DMA_EN	(1<<30)		/* SCC0A receive DMA enable */
117 #define IO_SSR_RES_27		(1<<27)		/* unused */
118 #define IO_SSR_RES_26		(1<<26)		/* unused */
119 #define IO_SSR_RES_25		(1<<25)		/* unused */
120 #define IO_SSR_RES_24		(1<<24)		/* unused */
121 #define IO_SSR_RES_23		(1<<23)		/* unused */
122 #define IO_SSR_SCSI_DMA_DIR	(1<<18)		/* SCSI DMA direction */
123 #define IO_SSR_SCSI_DMA_EN	(1<<17)		/* SCSI DMA enable */
124 #define IO_SSR_LANCE_DMA_EN	(1<<16)		/* LANCE DMA enable */
125 
126 						/* except Maxine */
127 #define IO_SSR_SCC1A_TX_DMA_EN	(1<<29)		/* SCC1A transmit DMA enable */
128 #define IO_SSR_SCC1A_RX_DMA_EN	(1<<28)		/* SCC1A receive DMA enable */
129 #define IO_SSR_RES_22		(1<<22)		/* unused */
130 #define IO_SSR_RES_21		(1<<21)		/* unused */
131 #define IO_SSR_RES_20		(1<<20)		/* unused */
132 #define IO_SSR_RES_19		(1<<19)		/* unused */
133 
134 						/* Maxine */
135 #define IO_SSR_AB_TX_DMA_EN	(1<<29)		/* ACCESS.bus xmit DMA enable */
136 #define IO_SSR_AB_RX_DMA_EN	(1<<28)		/* ACCESS.bus recv DMA enable */
137 #define IO_SSR_FLOPPY_DMA_DIR	(1<<22)		/* Floppy DMA direction */
138 #define IO_SSR_FLOPPY_DMA_EN	(1<<21)		/* Floppy DMA enable */
139 #define IO_SSR_ISDN_TX_DMA_EN	(1<<20)		/* ISDN transmit DMA enable */
140 #define IO_SSR_ISDN_RX_DMA_EN	(1<<19)		/* ISDN receive DMA enable */
141 
142 /*
143  * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
144  * defined here.  The rest is defined in system-specific headers.
145  */
146 #define KN0X_IO_SSR_DIAGDN	(1<<15)		/* diagnostic jumper */
147 #define KN0X_IO_SSR_SCC_RST	(1<<11)		/* ~SCC0,1 (Z85C30) reset */
148 #define KN0X_IO_SSR_RTC_RST	(1<<10)		/* ~RTC (DS1287) reset */
149 #define KN0X_IO_SSR_ASC_RST	(1<<9)		/* ~ASC (NCR53C94) reset */
150 #define KN0X_IO_SSR_LANCE_RST	(1<<8)		/* ~LANCE (Am7990) reset */
151 
152 #endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
153