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1 #ifndef __MACH_URQUELL_H
2 #define __MACH_URQUELL_H
3 
4 /*
5  * ------ 0x00000000 ------------------------------------
6  *  CS0 | (SW1,SW47)    EEPROM, SRAM, NOR FLASH
7  * -----+ 0x04000000 ------------------------------------
8  *  CS1 | (SW47)        SRAM, SRAM-LAN-PCMCIA, NOR FLASH
9  * -----+ 0x08000000 ------------------------------------
10  *  CS2 |               DDR3
11  *  CS3 |
12  * -----+ 0x10000000 ------------------------------------
13  *  CS4 |               PCIe
14  * -----+ 0x14000000 ------------------------------------
15  *  CS5 | (SW47)        LRAM/URAM, SRAM-LAN-PCMCIA
16  * -----+ 0x18000000 ------------------------------------
17  *  CS6 |               ATA, NAND FLASH
18  * -----+ 0x1c000000 ------------------------------------
19  *  CS7 |               SH7786 register
20  * -----+------------------------------------------------
21  */
22 
23 #define NOR_FLASH_ADDR	0x00000000
24 #define NOR_FLASH_SIZE	0x04000000
25 
26 #define CS1_BASE	0x05000000
27 #define CS5_BASE	0x15000000
28 #define FPGA_BASE	CS1_BASE
29 
30 #define BOARDREG(ofs)	(FPGA_BASE + ofs##_OFS)
31 #define UBOARDREG(ofs)	(0xa0000000 + FPGA_BASE + ofs##_OFS)
32 
33 #define SRSTR_OFS	0x0000 /* System reset register */
34 #define BDMR_OFS	0x0010 /* Board operating mode resister */
35 #define IRL0SR_OFS	0x0020 /* IRL0 Status register */
36 #define IRL0MSKR_OFS	0x0030 /* IRL0 Mask register */
37 #define IRL1SR_OFS	0x0040 /* IRL1 Status register */
38 #define IRL1MSKR_OFS	0x0050 /* IRL1 Mask register */
39 #define IRL2SR_OFS	0x0060 /* IRL2 Status register */
40 #define IRL2MSKR_OFS	0x0070 /* IRL2 Mask register */
41 #define IRL3SR_OFS	0x0080 /* IRL3 Status register */
42 #define IRL3MSKR_OFS	0x0090 /* IRL3 Mask register */
43 #define SOFTINTR_OFS	0x0120 /* Softwear Interrupt register */
44 #define SLEDR_OFS	0x0130 /* LED control resister */
45 #define MAPSCIFSWR_OFS	0x0140 /* Map/SCIF Switch register */
46 #define FPVERR_OFS	0x0150 /* FPGA Version register */
47 #define FPDATER_OFS	0x0160 /* FPGA Date register */
48 #define FPYEARR_OFS	0x0170 /* FPGA Year register */
49 #define TCLKCR_OFS	0x0180 /* TCLK Control register */
50 #define DIPSWMR_OFS	0x1000 /* DIPSW monitor register */
51 #define FPODR_OFS	0x1010 /* Output port data register */
52 #define ATACNR_OFS	0x1020 /* ATA-CN Control/status register */
53 #define FPINDR_OFS	0x1030 /* Input port data register */
54 #define MDSWMR_OFS	0x1040 /* MODE SW monitor register */
55 #define DDR3BUPCR_OFS	0x1050 /* DDR3 Backup control register */
56 #define SSICODECCR_OFS	0x1060 /* SSI-CODEC control register */
57 #define PCIESLOTSR_OFS	0x1070 /* PCIexpress Slot status register */
58 #define ETHERPORTSR_OFS	0x1080 /* EtherPhy Port status register */
59 #define LATCHCR_OFS	0x3000 /* Latch control register */
60 #define LATCUAR_OFS	0x3010 /* Latch upper address register */
61 #define LATCLAR_OFS	0x3012 /* Latch lower address register */
62 #define LATCLUDR_OFS	0x3024 /* Latch D31-16 register */
63 #define LATCLLDR_OFS	0x3026 /* Latch D15-0 register */
64 
65 #define CHARLED_OFS	0x2000 /* Character LED */
66 
67 #endif  /* __MACH_URQUELL_H */
68 
69