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Searched refs:IRQ_SPORT0_TX (Results 1 – 24 of 24) sorted by relevance

/arch/blackfin/mach-bf537/
DKconfig28 config IRQ_SPORT0_TX config
29 int "IRQ_SPORT0_TX"
Ddma.c64 ret_irq = IRQ_SPORT0_TX; in channel2irq()
/arch/blackfin/mach-bf533/
Ddma.c44 ret_irq = IRQ_SPORT0_TX; in channel2irq()
/arch/blackfin/mach-bf518/
Ddma.c64 ret_irq = IRQ_SPORT0_TX; in channel2irq()
DKconfig197 config IRQ_SPORT0_TX config
198 int "IRQ_SPORT0_TX"
/arch/blackfin/mach-bf527/
Ddma.c64 ret_irq = IRQ_SPORT0_TX; in channel2irq()
DKconfig196 config IRQ_SPORT0_TX config
197 int "IRQ_SPORT0_TX"
/arch/blackfin/mach-bf538/
DKconfig40 config IRQ_SPORT0_TX config
41 int "IRQ_SPORT0_TX"
Ddma.c84 ret_irq = IRQ_SPORT0_TX; in channel2irq()
/arch/blackfin/mach-bf533/include/mach/
Dirq.h24 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */ macro
/arch/blackfin/mach-bf561/
Ddma.c69 ret_irq = IRQ_SPORT0_TX; in channel2irq()
/arch/blackfin/mach-bf548/
Ddma.c59 ret_irq = IRQ_SPORT0_TX; in channel2irq()
DKconfig137 config IRQ_SPORT0_TX config
138 int "IRQ_SPORT0_TX"
/arch/blackfin/mach-bf538/include/mach/
Dirq.h24 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */ macro
/arch/blackfin/mach-bf537/include/mach/
Dirq.h20 #define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */ macro
/arch/blackfin/mach-bf518/include/mach/
Dirq.h30 #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ macro
/arch/blackfin/mach-bf527/include/mach/
Dirq.h29 #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ macro
/arch/blackfin/mach-bf609/
Ddma.c74 ret_irq = IRQ_SPORT0_TX; in channel2irq()
/arch/blackfin/mach-bf561/include/mach/
Dirq.h45 #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ macro
/arch/blackfin/mach-bf533/boards/
Dstamp.c453 .start = IRQ_SPORT0_TX,
454 .end = IRQ_SPORT0_TX+1,
/arch/blackfin/mach-bf537/boards/
Dcm_bf537e.c667 .start = IRQ_SPORT0_TX,
668 .end = IRQ_SPORT0_TX+1,
Dstamp.c2427 .start = IRQ_SPORT0_TX,
2428 .end = IRQ_SPORT0_TX+1,
/arch/blackfin/mach-bf609/include/mach/
Dirq.h59 #define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */ macro
/arch/blackfin/mach-bf548/include/mach/
Dirq.h24 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ macro