Searched refs:IV (Results 1 – 5 of 5) sorted by relevance
| /arch/x86/crypto/sha-mb/ |
| D | sha1_mb_mgr_datastruct.S | 63 #FIELD _IV, 16, 8 # IV
82 # RES_DQ .IV, 1
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| /arch/x86/crypto/ |
| D | aesni-intel_asm.S | 119 #define IV %xmm3 macro
2470 movups (IVP), IV
2491 pxor IV, STATE1
2496 movaps IN4, IV
2499 movaps IN2, IV
2521 pxor IV, STATE
2523 movaps IN, IV
2530 movups IV, (IVP)
2560 movaps IV, CTR
2592 movaps CTR, IV
[all …]
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| /arch/arm/crypto/ |
| D | aesbs-core.S_shipped | 1076 ldr r8, [ip] @ IV is 1st arg on the stack
1078 sub sp, #0x10 @ scratch space to carry over the IV
1117 vld1.8 {q15}, [r8] @ load IV
1136 vstmia r9, {q15} @ put aside IV
1140 vldmia r9, {q14} @ reload IV
1142 veor q0, q0, q14 @ ^= IV
1177 vstmia r9, {q15} @ put aside IV
1194 vldmia r9, {q14} @ reload IV
1196 veor q0, q0, q14 @ ^= IV
1217 vldmia r9,{q14} @ reload IV
[all …]
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| D | aes-ce-core.S | 385 @ Encrypt the IV in q0 with the second AES key. This should only
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| /arch/mips/ |
| D | Kconfig | 1617 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
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