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/arch/powerpc/net/
Dbpf_jit_comp.c111 #define CHOOSE_LOAD_FUNC(K, func) \ argument
112 ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
129 unsigned int K = filter[i].k; in bpf_jit_build_body() local
145 if (!K) in bpf_jit_build_body()
147 PPC_ADDI(r_A, r_A, IMM_L(K)); in bpf_jit_build_body()
148 if (K >= 32768) in bpf_jit_build_body()
149 PPC_ADDIS(r_A, r_A, IMM_HA(K)); in bpf_jit_build_body()
156 if (!K) in bpf_jit_build_body()
158 PPC_ADDI(r_A, r_A, IMM_L(-K)); in bpf_jit_build_body()
159 if (K >= 32768) in bpf_jit_build_body()
[all …]
/arch/sparc/net/
Dbpf_jit_comp.c91 #define SETHI(K, REG) \ argument
92 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
93 #define OR_LO(K, REG) \ argument
94 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
154 #define emit_set_const(K, REG) \ argument
156 *prog++ = SETHI(K, REG); \
158 *prog++ = OR_LO(K, REG); \
185 #define emit_alu_K(OPCODE, K) \ argument
187 if (K || OPCODE == AND || OPCODE == MUL) { \
190 if (is_simm13(K)) { \
[all …]
/arch/sparc/crypto/
Ddes_glue.c73 const u64 *K = ctx->encrypt_expkey; in des_encrypt() local
75 des_sparc64_crypt(K, (const u64 *) src, (u64 *) dst); in des_encrypt()
81 const u64 *K = ctx->decrypt_expkey; in des_decrypt() local
83 des_sparc64_crypt(K, (const u64 *) src, (u64 *) dst); in des_decrypt()
204 const u32 *K = (const u32 *)key; in des3_ede_set_key() local
210 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) || in des3_ede_set_key()
211 !((K[2] ^ K[4]) | (K[3] ^ K[5]))) && in des3_ede_set_key()
243 const u64 *K = ctx->encrypt_expkey; in des3_ede_encrypt() local
245 des3_ede_sparc64_crypt(K, (const u64 *) src, (u64 *) dst); in des3_ede_encrypt()
251 const u64 *K = ctx->decrypt_expkey; in des3_ede_decrypt() local
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/arch/mips/kvm/
D00README.txt5 Malta Board with FPGA based 34K
6 Sigma Designs TangoX board with a 24K based 8654 SoC.
7 Malta Board with 74K @ 1GHz
16 (2) 16K Page Sizes: Both Host Kernel and Guest Kernel should have the same page size, currently at …
17 Note that due to cache aliasing issues, 4K page sizes are NOT supported.
20 Both the host kernel and Guest kernel should have the page size set to 16K.
30 Currently KVM/MIPS emulates a 24K CPU without a FPU.
/arch/m68k/fpsp040/
Dslogn.S342 |--X = 2^(K) * Y, 1 <= Y < 2. THUS, Y = 1.XXXXXXXX....XX IN BINARY.
344 |--THE IDEA IS THAT LOG(X) = K*LOG2 + LOG(Y)
345 |-- = K*LOG2 + LOG(F) + LOG(1 + (Y-F)/F).
351 |--GET K, Y, F, AND ADDRESS OF 1/F.
354 subil #0x3FFF,%d0 | ...THIS IS K
355 addl ADJK(%a6),%d0 | ...ADJUST K, ORIGINAL INPUT MAY BE DENORM.
357 fmovel %d0,%fp1 | ...CONVERT K TO FLOATING-POINT FORMAT
360 movel #0x3FFF0000,X(%a6) | ...X IS NOW Y, I.E. 2^(-K)*X
376 |--SUMMARY: FP0 IS Y-F, A0 IS ADDRESS OF 1/F, FP1 IS K
382 fmulx LOGOF2,%fp1 | ...GET K*LOG2 WHILE FP0 IS NOT READY
[all …]
/arch/powerpc/boot/dts/
Dsbc8548-pre.dtsi38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
Damigaone.dts31 d-cache-size = <32768>; // L1, 32K
32 i-cache-size = <32768>; // L1, 32K
Dgef_sbc610.dts46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
Dmpc5125twr.dts41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
Dgef_ppc9a.dts46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
Dtqm5200.dts31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
Dtqm8xx.dts37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
/arch/x86/crypto/
Dsha512-avx-asm.S78 # W[t] + K[t] | W[t+1] + K[t+1]
105 # W[t]+K[t] (stack frame)
136 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
140 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
142 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
164 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
165 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
254 vpaddq K_t(idx), %xmm0, %xmm0 # Compute W[t]+K[t]
255 vmovdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
319 vpaddq K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
[all …]
Dsha512-ssse3-asm.S102 # W[t]+K[t] (stack frame)
129 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
133 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
135 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
158 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
159 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
261 paddq K_t(\rnd), %xmm0 # Compute W[t]+K[t]
264 movdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
318 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
326 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
[all …]
/arch/arc/include/asm/
Dentry-arcv2.h14 ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0)
25 ; - K mode: add the offset from current SP where H/w starts auto push
139 btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE
/arch/x86/crypto/sha-mb/
Dsha1_x8_avx2.S237 # ymm12 T6 K
267 K = %ymm12 define
369 vmovdqu K00_19(%rip), K
373 SHA1_STEP_00_15 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
382 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
388 vmovdqu K20_39(%rip), K
390 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F1
396 vmovdqu K40_59(%rip), K
398 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F2
404 vmovdqu K60_79(%rip), K
[all …]
/arch/arm/configs/
Dneponset_defconfig18 …8400n8 cpufreq=221200 rw root=/dev/mtdblock2 mtdparts=sa1100:512K(boot),1M(kernel),2560K(initrd),4…
/arch/mips/include/asm/mach-ip27/
Dkernel-entry-init.h51 dsrl t1, 12 # 4K pfn
52 dsrl t2, 12 # 4K pfn
/arch/arc/
DKconfig.debug9 kernel stack attached to each process/thread. The default is 8K.
/arch/sparc/kernel/
Ddtlb_miss.S2 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
Ditlb_miss.S2 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
/arch/arm/crypto/
Dsha512-core.S_shipped245 ldr r11,[r14,#LO] @ K[i].lo
247 ldr r12,[r14,#HI] @ K[i].hi
255 adc r4,r4,r12 @ T += K[i]
385 ldr r11,[r14,#LO] @ K[i].lo
387 ldr r12,[r14,#HI] @ K[i].hi
395 adc r4,r4,r12 @ T += K[i]
551 vld1.64 {d28},[r3,:64]! @ K[i++]
588 vld1.64 {d28},[r3,:64]! @ K[i++]
625 vld1.64 {d28},[r3,:64]! @ K[i++]
662 vld1.64 {d28},[r3,:64]! @ K[i++]
[all …]
Dsha512-armv4.pl501 my ($t0,$t1,$t2,$T1,$K,$Ch,$Maj)=map("d$_",(24..31)); # temps
515 vld1.64 {$K},[$Ktbl,:64]! @ K[i++]
532 vadd.i64 $K,@X[$i%16]
537 vadd.i64 $T1,$K
/arch/arc/kernel/
Dentry-arcv2.S172 ld r0, [sp, PT_status32] ; U/K mode at time of entry
186 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
192 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
/arch/arm64/kvm/
DKconfig41 We don't support KVM with 16K page tables yet, due to the multiple

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