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Searched refs:M32R_IRQ_SIO0_R (Results 1 – 10 of 10) sorted by relevance

/arch/m32r/platforms/oaks32r/
Dsetup.c90 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, in init_IRQ()
92 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
93 disable_oaks32r_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/m32104ut/
Dsetup.c93 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, in init_IRQ()
95 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; in init_IRQ()
96 disable_m32104ut_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/mappi/
Dsetup.c91 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, in init_IRQ()
93 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
94 disable_mappi_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/mappi2/
Dsetup.c92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, in init_IRQ()
94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
95 disable_mappi2_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/mappi3/
Dsetup.c91 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, in init_IRQ()
93 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
94 disable_mappi3_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/usrv/
Dsetup.c147 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, in init_IRQ()
149 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
150 disable_mappi_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/m32700ut/
Dsetup.c274 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, in init_IRQ()
276 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
277 disable_m32700ut_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/platforms/opsput/
Dsetup.c274 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, in init_IRQ()
276 icu_data[M32R_IRQ_SIO0_R].icucr = 0; in init_IRQ()
277 disable_opsput_irq(M32R_IRQ_SIO0_R); in init_IRQ()
/arch/m32r/include/asm/
Dm32102.h256 #define M32R_IRQ_SIO0_R (40) /* SIO0 send */ macro
269 #define M32R_IRQ_SIO0_R (48) /* SIO0 send */ macro
Dm32r_mp_fpga.h291 #define M32R_IRQ_SIO0_R (48) /* SIO0 receive */ macro