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Searched refs:MMCR0_PMC1SEL_SH (Results 1 – 2 of 2) sorted by relevance

/arch/powerpc/perf/
Dppc970-pmu.c45 #define MMCR0_PMC1SEL_SH 8 macro
388 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); in p970_compute_mmcr()
411 shift = MMCR0_PMC1SEL_SH - 7 * pmc; in p970_disable_pmc()
Dpower4-pmu.c48 #define MMCR0_PMC1SEL_SH 8 macro
504 mmcr0 |= psel << (MMCR0_PMC1SEL_SH - 7 * pmc); in p4_compute_mmcr()
535 mmcr[0] &= ~(0x1fUL << (MMCR0_PMC1SEL_SH - 7 * pmc)); in p4_disable_pmc()