1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 #include <linux/bits.h> 5 6 /* CPU model specific register (MSR) numbers */ 7 8 /* x86-64 specific MSRs */ 9 #define MSR_EFER 0xc0000080 /* extended feature register */ 10 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 11 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 12 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 13 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 14 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 15 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 16 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 17 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 18 19 /* EFER bits: */ 20 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 21 #define _EFER_LME 8 /* Long mode enable */ 22 #define _EFER_LMA 10 /* Long mode active (read-only) */ 23 #define _EFER_NX 11 /* No execute enable */ 24 #define _EFER_SVME 12 /* Enable virtualization */ 25 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 26 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 27 28 #define EFER_SCE (1<<_EFER_SCE) 29 #define EFER_LME (1<<_EFER_LME) 30 #define EFER_LMA (1<<_EFER_LMA) 31 #define EFER_NX (1<<_EFER_NX) 32 #define EFER_SVME (1<<_EFER_SVME) 33 #define EFER_LMSLE (1<<_EFER_LMSLE) 34 #define EFER_FFXSR (1<<_EFER_FFXSR) 35 36 /* Intel MSRs. Some also available on other CPUs */ 37 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 38 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 39 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 40 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 41 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 42 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 43 44 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 45 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 46 47 #define MSR_IA32_PERFCTR0 0x000000c1 48 #define MSR_IA32_PERFCTR1 0x000000c2 49 #define MSR_FSB_FREQ 0x000000cd 50 #define MSR_PLATFORM_INFO 0x000000ce 51 52 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 53 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 54 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 55 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 56 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 57 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 58 59 #define MSR_MTRRcap 0x000000fe 60 61 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 62 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 63 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 64 #define ARCH_CAP_SSB_NO BIT(4) /* 65 * Not susceptible to Speculative Store Bypass 66 * attack, so no Speculative Store Bypass 67 * control required. 68 */ 69 #define ARCH_CAP_MDS_NO BIT(5) /* 70 * Not susceptible to 71 * Microarchitectural Data 72 * Sampling (MDS) vulnerabilities. 73 */ 74 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 75 * The processor is not susceptible to a 76 * machine check error due to modifying the 77 * code page size along with either the 78 * physical address or cache type 79 * without TLB invalidation. 80 */ 81 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 82 #define ARCH_CAP_TAA_NO BIT(8) /* 83 * Not susceptible to 84 * TSX Async Abort (TAA) vulnerabilities. 85 */ 86 87 #define MSR_IA32_BBL_CR_CTL 0x00000119 88 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 89 90 #define MSR_IA32_TSX_CTRL 0x00000122 91 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 92 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 93 94 /* SRBDS support */ 95 #define MSR_IA32_MCU_OPT_CTRL 0x00000123 96 #define RNGDS_MITG_DIS BIT(0) 97 98 #define MSR_IA32_SYSENTER_CS 0x00000174 99 #define MSR_IA32_SYSENTER_ESP 0x00000175 100 #define MSR_IA32_SYSENTER_EIP 0x00000176 101 102 #define MSR_IA32_MCG_CAP 0x00000179 103 #define MSR_IA32_MCG_STATUS 0x0000017a 104 #define MSR_IA32_MCG_CTL 0x0000017b 105 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 106 107 #define MSR_OFFCORE_RSP_0 0x000001a6 108 #define MSR_OFFCORE_RSP_1 0x000001a7 109 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 110 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 111 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 112 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 113 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 114 115 #define MSR_LBR_SELECT 0x000001c8 116 #define MSR_LBR_TOS 0x000001c9 117 #define MSR_LBR_NHM_FROM 0x00000680 118 #define MSR_LBR_NHM_TO 0x000006c0 119 #define MSR_LBR_CORE_FROM 0x00000040 120 #define MSR_LBR_CORE_TO 0x00000060 121 122 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 123 #define LBR_INFO_MISPRED BIT_ULL(63) 124 #define LBR_INFO_IN_TX BIT_ULL(62) 125 #define LBR_INFO_ABORT BIT_ULL(61) 126 #define LBR_INFO_CYCLES 0xffff 127 128 #define MSR_IA32_PEBS_ENABLE 0x000003f1 129 #define MSR_IA32_DS_AREA 0x00000600 130 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 131 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 132 133 #define MSR_IA32_RTIT_CTL 0x00000570 134 #define RTIT_CTL_TRACEEN BIT(0) 135 #define RTIT_CTL_CYCLEACC BIT(1) 136 #define RTIT_CTL_OS BIT(2) 137 #define RTIT_CTL_USR BIT(3) 138 #define RTIT_CTL_CR3EN BIT(7) 139 #define RTIT_CTL_TOPA BIT(8) 140 #define RTIT_CTL_MTC_EN BIT(9) 141 #define RTIT_CTL_TSC_EN BIT(10) 142 #define RTIT_CTL_DISRETC BIT(11) 143 #define RTIT_CTL_BRANCH_EN BIT(13) 144 #define RTIT_CTL_MTC_RANGE_OFFSET 14 145 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 146 #define RTIT_CTL_CYC_THRESH_OFFSET 19 147 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 148 #define RTIT_CTL_PSB_FREQ_OFFSET 24 149 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 150 #define MSR_IA32_RTIT_STATUS 0x00000571 151 #define RTIT_STATUS_CONTEXTEN BIT(1) 152 #define RTIT_STATUS_TRIGGEREN BIT(2) 153 #define RTIT_STATUS_ERROR BIT(4) 154 #define RTIT_STATUS_STOPPED BIT(5) 155 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 156 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 157 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 158 159 #define MSR_MTRRfix64K_00000 0x00000250 160 #define MSR_MTRRfix16K_80000 0x00000258 161 #define MSR_MTRRfix16K_A0000 0x00000259 162 #define MSR_MTRRfix4K_C0000 0x00000268 163 #define MSR_MTRRfix4K_C8000 0x00000269 164 #define MSR_MTRRfix4K_D0000 0x0000026a 165 #define MSR_MTRRfix4K_D8000 0x0000026b 166 #define MSR_MTRRfix4K_E0000 0x0000026c 167 #define MSR_MTRRfix4K_E8000 0x0000026d 168 #define MSR_MTRRfix4K_F0000 0x0000026e 169 #define MSR_MTRRfix4K_F8000 0x0000026f 170 #define MSR_MTRRdefType 0x000002ff 171 172 #define MSR_IA32_CR_PAT 0x00000277 173 174 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 175 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 176 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 177 #define MSR_IA32_LASTINTFROMIP 0x000001dd 178 #define MSR_IA32_LASTINTTOIP 0x000001de 179 180 /* DEBUGCTLMSR bits (others vary by model): */ 181 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 182 #define DEBUGCTLMSR_BTF_SHIFT 1 183 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 184 #define DEBUGCTLMSR_TR (1UL << 6) 185 #define DEBUGCTLMSR_BTS (1UL << 7) 186 #define DEBUGCTLMSR_BTINT (1UL << 8) 187 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 188 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 189 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 190 191 #define MSR_PEBS_FRONTEND 0x000003f7 192 193 #define MSR_IA32_POWER_CTL 0x000001fc 194 195 #define MSR_IA32_MC0_CTL 0x00000400 196 #define MSR_IA32_MC0_STATUS 0x00000401 197 #define MSR_IA32_MC0_ADDR 0x00000402 198 #define MSR_IA32_MC0_MISC 0x00000403 199 200 /* C-state Residency Counters */ 201 #define MSR_PKG_C3_RESIDENCY 0x000003f8 202 #define MSR_PKG_C6_RESIDENCY 0x000003f9 203 #define MSR_PKG_C7_RESIDENCY 0x000003fa 204 #define MSR_CORE_C3_RESIDENCY 0x000003fc 205 #define MSR_CORE_C6_RESIDENCY 0x000003fd 206 #define MSR_CORE_C7_RESIDENCY 0x000003fe 207 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 208 #define MSR_PKG_C2_RESIDENCY 0x0000060d 209 #define MSR_PKG_C8_RESIDENCY 0x00000630 210 #define MSR_PKG_C9_RESIDENCY 0x00000631 211 #define MSR_PKG_C10_RESIDENCY 0x00000632 212 213 /* Run Time Average Power Limiting (RAPL) Interface */ 214 215 #define MSR_RAPL_POWER_UNIT 0x00000606 216 217 #define MSR_PKG_POWER_LIMIT 0x00000610 218 #define MSR_PKG_ENERGY_STATUS 0x00000611 219 #define MSR_PKG_PERF_STATUS 0x00000613 220 #define MSR_PKG_POWER_INFO 0x00000614 221 222 #define MSR_DRAM_POWER_LIMIT 0x00000618 223 #define MSR_DRAM_ENERGY_STATUS 0x00000619 224 #define MSR_DRAM_PERF_STATUS 0x0000061b 225 #define MSR_DRAM_POWER_INFO 0x0000061c 226 227 #define MSR_PP0_POWER_LIMIT 0x00000638 228 #define MSR_PP0_ENERGY_STATUS 0x00000639 229 #define MSR_PP0_POLICY 0x0000063a 230 #define MSR_PP0_PERF_STATUS 0x0000063b 231 232 #define MSR_PP1_POWER_LIMIT 0x00000640 233 #define MSR_PP1_ENERGY_STATUS 0x00000641 234 #define MSR_PP1_POLICY 0x00000642 235 236 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 237 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 238 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 239 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 240 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 241 242 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 243 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 244 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 245 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 246 247 #define MSR_CORE_C1_RES 0x00000660 248 249 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 250 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 251 252 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 253 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 254 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 255 256 /* Config TDP MSRs */ 257 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 258 #define MSR_CONFIG_TDP_LEVEL1 0x00000649 259 #define MSR_CONFIG_TDP_LEVEL2 0x0000064A 260 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 261 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 262 263 /* Hardware P state interface */ 264 #define MSR_PPERF 0x0000064e 265 #define MSR_PERF_LIMIT_REASONS 0x0000064f 266 #define MSR_PM_ENABLE 0x00000770 267 #define MSR_HWP_CAPABILITIES 0x00000771 268 #define MSR_HWP_REQUEST_PKG 0x00000772 269 #define MSR_HWP_INTERRUPT 0x00000773 270 #define MSR_HWP_REQUEST 0x00000774 271 #define MSR_HWP_STATUS 0x00000777 272 273 /* CPUID.6.EAX */ 274 #define HWP_BASE_BIT (1<<7) 275 #define HWP_NOTIFICATIONS_BIT (1<<8) 276 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 277 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 278 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 279 280 /* IA32_HWP_CAPABILITIES */ 281 #define HWP_HIGHEST_PERF(x) (x & 0xff) 282 #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) 283 #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) 284 #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) 285 286 /* IA32_HWP_REQUEST */ 287 #define HWP_MIN_PERF(x) (x & 0xff) 288 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 289 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 290 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 291 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 292 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 293 294 /* IA32_HWP_STATUS */ 295 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 296 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 297 298 /* IA32_HWP_INTERRUPT */ 299 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 300 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 301 302 #define MSR_AMD64_MC0_MASK 0xc0010044 303 304 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 305 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 306 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 307 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 308 309 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 310 311 /* These are consecutive and not in the normal 4er MCE bank block */ 312 #define MSR_IA32_MC0_CTL2 0x00000280 313 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 314 315 #define MSR_P6_PERFCTR0 0x000000c1 316 #define MSR_P6_PERFCTR1 0x000000c2 317 #define MSR_P6_EVNTSEL0 0x00000186 318 #define MSR_P6_EVNTSEL1 0x00000187 319 320 #define MSR_KNC_PERFCTR0 0x00000020 321 #define MSR_KNC_PERFCTR1 0x00000021 322 #define MSR_KNC_EVNTSEL0 0x00000028 323 #define MSR_KNC_EVNTSEL1 0x00000029 324 325 /* Alternative perfctr range with full access. */ 326 #define MSR_IA32_PMC0 0x000004c1 327 328 /* AMD64 MSRs. Not complete. See the architecture manual for a more 329 complete list. */ 330 331 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 332 #define MSR_AMD64_TSC_RATIO 0xc0000104 333 #define MSR_AMD64_NB_CFG 0xc001001f 334 #define MSR_AMD64_CPUID_FN_1 0xc0011004 335 #define MSR_AMD64_PATCH_LOADER 0xc0010020 336 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 337 #define MSR_AMD64_OSVW_STATUS 0xc0010141 338 #define MSR_AMD64_LS_CFG 0xc0011020 339 #define MSR_AMD64_DC_CFG 0xc0011022 340 #define MSR_AMD64_BU_CFG2 0xc001102a 341 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 342 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 343 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 344 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 345 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 346 #define MSR_AMD64_IBSOPCTL 0xc0011033 347 #define MSR_AMD64_IBSOPRIP 0xc0011034 348 #define MSR_AMD64_IBSOPDATA 0xc0011035 349 #define MSR_AMD64_IBSOPDATA2 0xc0011036 350 #define MSR_AMD64_IBSOPDATA3 0xc0011037 351 #define MSR_AMD64_IBSDCLINAD 0xc0011038 352 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 353 #define MSR_AMD64_IBSOP_REG_COUNT 7 354 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 355 #define MSR_AMD64_IBSCTL 0xc001103a 356 #define MSR_AMD64_IBSBRTARGET 0xc001103b 357 #define MSR_AMD64_IBSOPDATA4 0xc001103d 358 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 359 360 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 361 362 /* Fam 16h MSRs */ 363 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 364 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 365 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 366 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 367 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 368 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 369 370 /* Fam 15h MSRs */ 371 #define MSR_F15H_PERF_CTL 0xc0010200 372 #define MSR_F15H_PERF_CTR 0xc0010201 373 #define MSR_F15H_NB_PERF_CTL 0xc0010240 374 #define MSR_F15H_NB_PERF_CTR 0xc0010241 375 376 /* Fam 10h MSRs */ 377 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 378 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 379 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 380 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 381 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 382 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 383 #define MSR_FAM10H_NODE_ID 0xc001100c 384 #define MSR_F10H_DECFG 0xc0011029 385 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 386 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 387 388 /* K8 MSRs */ 389 #define MSR_K8_TOP_MEM1 0xc001001a 390 #define MSR_K8_TOP_MEM2 0xc001001d 391 #define MSR_K8_SYSCFG 0xc0010010 392 #define MSR_K8_INT_PENDING_MSG 0xc0010055 393 /* C1E active bits in int pending message */ 394 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 395 #define MSR_K8_TSEG_ADDR 0xc0010112 396 #define MSR_K8_TSEG_MASK 0xc0010113 397 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 398 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 399 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 400 401 /* K7 MSRs */ 402 #define MSR_K7_EVNTSEL0 0xc0010000 403 #define MSR_K7_PERFCTR0 0xc0010004 404 #define MSR_K7_EVNTSEL1 0xc0010001 405 #define MSR_K7_PERFCTR1 0xc0010005 406 #define MSR_K7_EVNTSEL2 0xc0010002 407 #define MSR_K7_PERFCTR2 0xc0010006 408 #define MSR_K7_EVNTSEL3 0xc0010003 409 #define MSR_K7_PERFCTR3 0xc0010007 410 #define MSR_K7_CLK_CTL 0xc001001b 411 #define MSR_K7_HWCR 0xc0010015 412 #define MSR_K7_FID_VID_CTL 0xc0010041 413 #define MSR_K7_FID_VID_STATUS 0xc0010042 414 415 /* K6 MSRs */ 416 #define MSR_K6_WHCR 0xc0000082 417 #define MSR_K6_UWCCR 0xc0000085 418 #define MSR_K6_EPMR 0xc0000086 419 #define MSR_K6_PSOR 0xc0000087 420 #define MSR_K6_PFIR 0xc0000088 421 422 /* Centaur-Hauls/IDT defined MSRs. */ 423 #define MSR_IDT_FCR1 0x00000107 424 #define MSR_IDT_FCR2 0x00000108 425 #define MSR_IDT_FCR3 0x00000109 426 #define MSR_IDT_FCR4 0x0000010a 427 428 #define MSR_IDT_MCR0 0x00000110 429 #define MSR_IDT_MCR1 0x00000111 430 #define MSR_IDT_MCR2 0x00000112 431 #define MSR_IDT_MCR3 0x00000113 432 #define MSR_IDT_MCR4 0x00000114 433 #define MSR_IDT_MCR5 0x00000115 434 #define MSR_IDT_MCR6 0x00000116 435 #define MSR_IDT_MCR7 0x00000117 436 #define MSR_IDT_MCR_CTRL 0x00000120 437 438 /* VIA Cyrix defined MSRs*/ 439 #define MSR_VIA_FCR 0x00001107 440 #define MSR_VIA_LONGHAUL 0x0000110a 441 #define MSR_VIA_RNG 0x0000110b 442 #define MSR_VIA_BCR2 0x00001147 443 444 /* Transmeta defined MSRs */ 445 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 446 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 447 #define MSR_TMTA_LRTI_READOUT 0x80868018 448 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 449 450 /* Intel defined MSRs. */ 451 #define MSR_IA32_P5_MC_ADDR 0x00000000 452 #define MSR_IA32_P5_MC_TYPE 0x00000001 453 #define MSR_IA32_TSC 0x00000010 454 #define MSR_IA32_PLATFORM_ID 0x00000017 455 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 456 #define MSR_EBC_FREQUENCY_ID 0x0000002c 457 #define MSR_SMI_COUNT 0x00000034 458 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 459 #define MSR_IA32_TSC_ADJUST 0x0000003b 460 #define MSR_IA32_BNDCFGS 0x00000d90 461 462 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 463 464 #define MSR_IA32_XSS 0x00000da0 465 466 #define FEATURE_CONTROL_LOCKED (1<<0) 467 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 468 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 469 #define FEATURE_CONTROL_LMCE (1<<20) 470 471 #define MSR_IA32_APICBASE 0x0000001b 472 #define MSR_IA32_APICBASE_BSP (1<<8) 473 #define MSR_IA32_APICBASE_ENABLE (1<<11) 474 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 475 476 #define MSR_IA32_TSCDEADLINE 0x000006e0 477 478 #define MSR_IA32_UCODE_WRITE 0x00000079 479 #define MSR_IA32_UCODE_REV 0x0000008b 480 481 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 482 #define MSR_IA32_SMBASE 0x0000009e 483 484 #define MSR_IA32_PERF_STATUS 0x00000198 485 #define MSR_IA32_PERF_CTL 0x00000199 486 #define INTEL_PERF_CTL_MASK 0xffff 487 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 488 #define MSR_AMD_PERF_STATUS 0xc0010063 489 #define MSR_AMD_PERF_CTL 0xc0010062 490 491 #define MSR_IA32_MPERF 0x000000e7 492 #define MSR_IA32_APERF 0x000000e8 493 494 #define MSR_IA32_THERM_CONTROL 0x0000019a 495 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 496 497 #define THERM_INT_HIGH_ENABLE (1 << 0) 498 #define THERM_INT_LOW_ENABLE (1 << 1) 499 #define THERM_INT_PLN_ENABLE (1 << 24) 500 501 #define MSR_IA32_THERM_STATUS 0x0000019c 502 503 #define THERM_STATUS_PROCHOT (1 << 0) 504 #define THERM_STATUS_POWER_LIMIT (1 << 10) 505 506 #define MSR_THERM2_CTL 0x0000019d 507 508 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 509 510 #define MSR_IA32_MISC_ENABLE 0x000001a0 511 512 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 513 514 #define MSR_MISC_PWR_MGMT 0x000001aa 515 516 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 517 #define ENERGY_PERF_BIAS_PERFORMANCE 0 518 #define ENERGY_PERF_BIAS_NORMAL 6 519 #define ENERGY_PERF_BIAS_POWERSAVE 15 520 521 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 522 523 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 524 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 525 526 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 527 528 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 529 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 530 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 531 532 /* Thermal Thresholds Support */ 533 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 534 #define THERM_SHIFT_THRESHOLD0 8 535 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 536 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 537 #define THERM_SHIFT_THRESHOLD1 16 538 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 539 #define THERM_STATUS_THRESHOLD0 (1 << 6) 540 #define THERM_LOG_THRESHOLD0 (1 << 7) 541 #define THERM_STATUS_THRESHOLD1 (1 << 8) 542 #define THERM_LOG_THRESHOLD1 (1 << 9) 543 544 /* MISC_ENABLE bits: architectural */ 545 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 546 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 547 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 548 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 549 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 550 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 551 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 552 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 553 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 554 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 555 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 556 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 557 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 558 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 559 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 560 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 561 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 562 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 563 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 564 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 565 566 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 567 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 568 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 569 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 570 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 571 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 572 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 573 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 574 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 575 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 576 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 577 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 578 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 579 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 580 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 581 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 582 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 583 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 584 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 585 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 586 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 587 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 588 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 589 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 590 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 591 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 592 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 593 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 594 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 595 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 596 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 597 598 #define MSR_IA32_TSC_DEADLINE 0x000006E0 599 600 /* P4/Xeon+ specific */ 601 #define MSR_IA32_MCG_EAX 0x00000180 602 #define MSR_IA32_MCG_EBX 0x00000181 603 #define MSR_IA32_MCG_ECX 0x00000182 604 #define MSR_IA32_MCG_EDX 0x00000183 605 #define MSR_IA32_MCG_ESI 0x00000184 606 #define MSR_IA32_MCG_EDI 0x00000185 607 #define MSR_IA32_MCG_EBP 0x00000186 608 #define MSR_IA32_MCG_ESP 0x00000187 609 #define MSR_IA32_MCG_EFLAGS 0x00000188 610 #define MSR_IA32_MCG_EIP 0x00000189 611 #define MSR_IA32_MCG_RESERVED 0x0000018a 612 613 /* Pentium IV performance counter MSRs */ 614 #define MSR_P4_BPU_PERFCTR0 0x00000300 615 #define MSR_P4_BPU_PERFCTR1 0x00000301 616 #define MSR_P4_BPU_PERFCTR2 0x00000302 617 #define MSR_P4_BPU_PERFCTR3 0x00000303 618 #define MSR_P4_MS_PERFCTR0 0x00000304 619 #define MSR_P4_MS_PERFCTR1 0x00000305 620 #define MSR_P4_MS_PERFCTR2 0x00000306 621 #define MSR_P4_MS_PERFCTR3 0x00000307 622 #define MSR_P4_FLAME_PERFCTR0 0x00000308 623 #define MSR_P4_FLAME_PERFCTR1 0x00000309 624 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 625 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 626 #define MSR_P4_IQ_PERFCTR0 0x0000030c 627 #define MSR_P4_IQ_PERFCTR1 0x0000030d 628 #define MSR_P4_IQ_PERFCTR2 0x0000030e 629 #define MSR_P4_IQ_PERFCTR3 0x0000030f 630 #define MSR_P4_IQ_PERFCTR4 0x00000310 631 #define MSR_P4_IQ_PERFCTR5 0x00000311 632 #define MSR_P4_BPU_CCCR0 0x00000360 633 #define MSR_P4_BPU_CCCR1 0x00000361 634 #define MSR_P4_BPU_CCCR2 0x00000362 635 #define MSR_P4_BPU_CCCR3 0x00000363 636 #define MSR_P4_MS_CCCR0 0x00000364 637 #define MSR_P4_MS_CCCR1 0x00000365 638 #define MSR_P4_MS_CCCR2 0x00000366 639 #define MSR_P4_MS_CCCR3 0x00000367 640 #define MSR_P4_FLAME_CCCR0 0x00000368 641 #define MSR_P4_FLAME_CCCR1 0x00000369 642 #define MSR_P4_FLAME_CCCR2 0x0000036a 643 #define MSR_P4_FLAME_CCCR3 0x0000036b 644 #define MSR_P4_IQ_CCCR0 0x0000036c 645 #define MSR_P4_IQ_CCCR1 0x0000036d 646 #define MSR_P4_IQ_CCCR2 0x0000036e 647 #define MSR_P4_IQ_CCCR3 0x0000036f 648 #define MSR_P4_IQ_CCCR4 0x00000370 649 #define MSR_P4_IQ_CCCR5 0x00000371 650 #define MSR_P4_ALF_ESCR0 0x000003ca 651 #define MSR_P4_ALF_ESCR1 0x000003cb 652 #define MSR_P4_BPU_ESCR0 0x000003b2 653 #define MSR_P4_BPU_ESCR1 0x000003b3 654 #define MSR_P4_BSU_ESCR0 0x000003a0 655 #define MSR_P4_BSU_ESCR1 0x000003a1 656 #define MSR_P4_CRU_ESCR0 0x000003b8 657 #define MSR_P4_CRU_ESCR1 0x000003b9 658 #define MSR_P4_CRU_ESCR2 0x000003cc 659 #define MSR_P4_CRU_ESCR3 0x000003cd 660 #define MSR_P4_CRU_ESCR4 0x000003e0 661 #define MSR_P4_CRU_ESCR5 0x000003e1 662 #define MSR_P4_DAC_ESCR0 0x000003a8 663 #define MSR_P4_DAC_ESCR1 0x000003a9 664 #define MSR_P4_FIRM_ESCR0 0x000003a4 665 #define MSR_P4_FIRM_ESCR1 0x000003a5 666 #define MSR_P4_FLAME_ESCR0 0x000003a6 667 #define MSR_P4_FLAME_ESCR1 0x000003a7 668 #define MSR_P4_FSB_ESCR0 0x000003a2 669 #define MSR_P4_FSB_ESCR1 0x000003a3 670 #define MSR_P4_IQ_ESCR0 0x000003ba 671 #define MSR_P4_IQ_ESCR1 0x000003bb 672 #define MSR_P4_IS_ESCR0 0x000003b4 673 #define MSR_P4_IS_ESCR1 0x000003b5 674 #define MSR_P4_ITLB_ESCR0 0x000003b6 675 #define MSR_P4_ITLB_ESCR1 0x000003b7 676 #define MSR_P4_IX_ESCR0 0x000003c8 677 #define MSR_P4_IX_ESCR1 0x000003c9 678 #define MSR_P4_MOB_ESCR0 0x000003aa 679 #define MSR_P4_MOB_ESCR1 0x000003ab 680 #define MSR_P4_MS_ESCR0 0x000003c0 681 #define MSR_P4_MS_ESCR1 0x000003c1 682 #define MSR_P4_PMH_ESCR0 0x000003ac 683 #define MSR_P4_PMH_ESCR1 0x000003ad 684 #define MSR_P4_RAT_ESCR0 0x000003bc 685 #define MSR_P4_RAT_ESCR1 0x000003bd 686 #define MSR_P4_SAAT_ESCR0 0x000003ae 687 #define MSR_P4_SAAT_ESCR1 0x000003af 688 #define MSR_P4_SSU_ESCR0 0x000003be 689 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 690 691 #define MSR_P4_TBPU_ESCR0 0x000003c2 692 #define MSR_P4_TBPU_ESCR1 0x000003c3 693 #define MSR_P4_TC_ESCR0 0x000003c4 694 #define MSR_P4_TC_ESCR1 0x000003c5 695 #define MSR_P4_U2L_ESCR0 0x000003b0 696 #define MSR_P4_U2L_ESCR1 0x000003b1 697 698 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 699 700 /* Intel Core-based CPU performance counters */ 701 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 702 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 703 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 704 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 705 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 706 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 707 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 708 709 /* Geode defined MSRs */ 710 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 711 712 /* Intel VT MSRs */ 713 #define MSR_IA32_VMX_BASIC 0x00000480 714 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 715 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 716 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 717 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 718 #define MSR_IA32_VMX_MISC 0x00000485 719 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 720 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 721 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 722 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 723 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 724 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 725 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 726 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 727 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 728 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 729 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 730 #define MSR_IA32_VMX_VMFUNC 0x00000491 731 732 /* VMX_BASIC bits and bitmasks */ 733 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 734 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 735 #define VMX_BASIC_64 0x0001000000000000LLU 736 #define VMX_BASIC_MEM_TYPE_SHIFT 50 737 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 738 #define VMX_BASIC_MEM_TYPE_WB 6LLU 739 #define VMX_BASIC_INOUT 0x0040000000000000LLU 740 741 /* MSR_IA32_VMX_MISC bits */ 742 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 743 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 744 /* AMD-V MSRs */ 745 746 #define MSR_VM_CR 0xc0010114 747 #define MSR_VM_IGNNE 0xc0010115 748 #define MSR_VM_HSAVE_PA 0xc0010117 749 750 #endif /* _ASM_X86_MSR_INDEX_H */ 751