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Searched refs:MSR_P4_TBPU_ESCR1 (Results 1 – 3 of 3) sorted by relevance

/arch/x86/oprofile/
Dop_model_p4.c334 { CTR_MS_2, MSR_P4_TBPU_ESCR1} }
340 { CTR_MS_2, MSR_P4_TBPU_ESCR1} }
/arch/x86/include/asm/
Dmsr-index.h692 #define MSR_P4_TBPU_ESCR1 0x000003c3 macro
/arch/x86/kernel/cpu/
Dperf_event_p4.c357 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
1171 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),