1 #ifndef _ASM_X86_MWAIT_H
2 #define _ASM_X86_MWAIT_H
3
4 #include <linux/sched.h>
5
6 #include <asm/cpufeature.h>
7 #include <asm/nospec-branch.h>
8
9 #define MWAIT_SUBSTATE_MASK 0xf
10 #define MWAIT_CSTATE_MASK 0xf
11 #define MWAIT_SUBSTATE_SIZE 4
12 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
13 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
14
15 #define CPUID_MWAIT_LEAF 5
16 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
17 #define CPUID5_ECX_INTERRUPT_BREAK 0x2
18
19 #define MWAIT_ECX_INTERRUPT_BREAK 0x1
20 #define MWAITX_ECX_TIMER_ENABLE BIT(1)
21 #define MWAITX_MAX_LOOPS ((u32)-1)
22 #define MWAITX_DISABLE_CSTATES 0xf0
23
__monitor(const void * eax,unsigned long ecx,unsigned long edx)24 static inline void __monitor(const void *eax, unsigned long ecx,
25 unsigned long edx)
26 {
27 /* "monitor %eax, %ecx, %edx;" */
28 asm volatile(".byte 0x0f, 0x01, 0xc8;"
29 :: "a" (eax), "c" (ecx), "d"(edx));
30 }
31
__monitorx(const void * eax,unsigned long ecx,unsigned long edx)32 static inline void __monitorx(const void *eax, unsigned long ecx,
33 unsigned long edx)
34 {
35 /* "monitorx %eax, %ecx, %edx;" */
36 asm volatile(".byte 0x0f, 0x01, 0xfa;"
37 :: "a" (eax), "c" (ecx), "d"(edx));
38 }
39
__mwait(unsigned long eax,unsigned long ecx)40 static inline void __mwait(unsigned long eax, unsigned long ecx)
41 {
42 mds_idle_clear_cpu_buffers();
43
44 /* "mwait %eax, %ecx;" */
45 asm volatile(".byte 0x0f, 0x01, 0xc9;"
46 :: "a" (eax), "c" (ecx));
47 }
48
49 /*
50 * MWAITX allows for a timer expiration to get the core out a wait state in
51 * addition to the default MWAIT exit condition of a store appearing at a
52 * monitored virtual address.
53 *
54 * Registers:
55 *
56 * MWAITX ECX[1]: enable timer if set
57 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
58 * frequency is the same as the TSC frequency.
59 *
60 * Below is a comparison between MWAIT and MWAITX on AMD processors:
61 *
62 * MWAIT MWAITX
63 * opcode 0f 01 c9 | 0f 01 fb
64 * ECX[0] value of RFLAGS.IF seen by instruction
65 * ECX[1] unused/#GP if set | enable timer if set
66 * ECX[31:2] unused/#GP if set
67 * EAX unused (reserve for hint)
68 * EBX[31:0] unused | max wait time (P0 clocks)
69 *
70 * MONITOR MONITORX
71 * opcode 0f 01 c8 | 0f 01 fa
72 * EAX (logical) address to monitor
73 * ECX #GP if not zero
74 */
__mwaitx(unsigned long eax,unsigned long ebx,unsigned long ecx)75 static inline void __mwaitx(unsigned long eax, unsigned long ebx,
76 unsigned long ecx)
77 {
78 /* No MDS buffer clear as this is AMD/HYGON only */
79
80 /* "mwaitx %eax, %ebx, %ecx;" */
81 asm volatile(".byte 0x0f, 0x01, 0xfb;"
82 :: "a" (eax), "b" (ebx), "c" (ecx));
83 }
84
__sti_mwait(unsigned long eax,unsigned long ecx)85 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
86 {
87 mds_idle_clear_cpu_buffers();
88
89 trace_hardirqs_on();
90 /* "mwait %eax, %ecx;" */
91 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
92 :: "a" (eax), "c" (ecx));
93 }
94
95 /*
96 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
97 * which can obviate IPI to trigger checking of need_resched.
98 * We execute MONITOR against need_resched and enter optimized wait state
99 * through MWAIT. Whenever someone changes need_resched, we would be woken
100 * up from MWAIT (without an IPI).
101 *
102 * New with Core Duo processors, MWAIT can take some hints based on CPU
103 * capability.
104 */
mwait_idle_with_hints(unsigned long eax,unsigned long ecx)105 static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
106 {
107 if (!current_set_polling_and_test()) {
108 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
109 mb();
110 clflush((void *)¤t_thread_info()->flags);
111 mb();
112 }
113
114 __monitor((void *)¤t_thread_info()->flags, 0, 0);
115 if (!need_resched())
116 __mwait(eax, ecx);
117 }
118 current_clr_polling();
119 }
120
121 #endif /* _ASM_X86_MWAIT_H */
122