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1 /*
2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17  * MA  02110-1301, USA.
18  */
19 
20 #ifndef __ASM_ARCH_MXC_IIM_H__
21 #define __ASM_ARCH_MXC_IIM_H__
22 
23 /* Register offsets */
24 #define MXC_IIMSTAT             0x0000
25 #define MXC_IIMSTATM            0x0004
26 #define MXC_IIMERR              0x0008
27 #define MXC_IIMEMASK            0x000C
28 #define MXC_IIMFCTL             0x0010
29 #define MXC_IIMUA               0x0014
30 #define MXC_IIMLA               0x0018
31 #define MXC_IIMSDAT             0x001C
32 #define MXC_IIMPREV             0x0020
33 #define MXC_IIMSREV             0x0024
34 #define MXC_IIMPRG_P            0x0028
35 #define MXC_IIMSCS0             0x002C
36 #define MXC_IIMSCS1             0x0030
37 #define MXC_IIMSCS2             0x0034
38 #define MXC_IIMSCS3             0x0038
39 #define MXC_IIMFBAC0            0x0800
40 #define MXC_IIMJAC              0x0804
41 #define MXC_IIMHWV1             0x0808
42 #define MXC_IIMHWV2             0x080C
43 #define MXC_IIMHAB0             0x0810
44 #define MXC_IIMHAB1             0x0814
45 /* Definitions for i.MX27 TO2 */
46 #define MXC_IIMMAC              0x0814
47 #define MXC_IIMPREV_FUSE        0x0818
48 #define MXC_IIMSREV_FUSE        0x081C
49 #define MXC_IIMSJC_CHALL_0      0x0820
50 #define MXC_IIMSJC_CHALL_7      0x083C
51 #define MXC_IIMFB0UC17          0x0840
52 #define MXC_IIMFB0UC255         0x0BFC
53 #define MXC_IIMFBAC1            0x0C00
54 /* Definitions for i.MX27 TO2 */
55 #define MXC_IIMSUID             0x0C04
56 #define MXC_IIMKEY0             0x0C04
57 #define MXC_IIMKEY20            0x0C54
58 #define MXC_IIMSJC_RESP_0       0x0C58
59 #define MXC_IIMSJC_RESP_7       0x0C74
60 #define MXC_IIMFB1UC30          0x0C78
61 #define MXC_IIMFB1UC255         0x0FFC
62 
63 /* Bit definitions */
64 
65 #define MXC_IIMHWV1_WLOCK               (0x1 << 7)
66 #define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
67 #define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
68 #define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
69 #define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
70 #define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
71 #define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
72 
73 #define MXC_IIMHWV2_WLOCK               (0x1 << 7)
74 #define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
75 #define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
76 
77 #endif /* __ASM_ARCH_MXC_IIM_H__ */
78