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Searched refs:MXVR_SYNC_LCHAN_5 (Results 1 – 5 of 5) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF549.h58 #define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Reg… macro
DcdefBF549.h92 #define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
93 #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h57 #define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ macro
DcdefBF539.h83 #define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
84 #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1171 D32(MXVR_SYNC_LCHAN_5); in bfin_debug_mmrs_init()